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IC Epson S1D13L01 LCD Controller

IC Epson S1D13L01 LCD Controller
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Hardware Functional Specification Document Number:XA8A-A-001-01 Issue Date: 02/28/14 SEIKO EPSON CORPORATION

NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is...

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Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Features . . . . 2.1 Display Resolution 2.2 CPU Interface . . 2.3 Input Data Format . 2.4 Display Interface . 2.5 Display Features . 2.6 Miscellaneous . . Chapter 3 Typical System Implementation . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 4 Pins . . . . . . . . . . . . . 4.1 Pinout Diagram ....

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Chapter 11 Indirect and Serial Host Interface Accessing Sequence . . . . 11.1 Indirect Interface . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Write Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 Write Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 12 Image Data Formats . . . . . . 12.1 Image Data...

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12.2 Data Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3 Color Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Chapter 13 Look-Up Table Architecture 13.1 24 bpp LUT . . . . . . . . . . 13.2 16 bpp LUT . . . . . . . . . . 13.3 8 bpp LUT in Color Mode . . . . Chapter 14 Display Features . . . . . . 14.1 PIP (Picture-in-Picture) Layer . . 14.2 Transparency . . . . . . . . . 14.3 Alpha Blending . . . . . . . . 14.4 PIP Effects . . . . . . . . . . 14.4.1 Blinking and Fading Effects . 14.4.2 Blink/Fade Period . . . . . . 14.4.3 Fade Steps ....

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S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Chapter 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13L01 Series Simple LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development. The latest revision can be downloaded at vdc.epson.com. We appreciate your comments on our documentation. Please...

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Chapter 2 Features 2.1 Display Resolution • 384K bytes of embedded VRAM for storing the image data • Display Resolutions for one layer display (Main Layer Only): • Up to 480x272 at 24 bpp • Up to 800x480 at 8 bpp • Display Resolutions for two layer display (Main and PIP Layer): • Up to 400x240 at 24 bpp (Main Layer) and 400x240 at 8 bpp (PIP Layer) 2.2 CPU Interface • 8/16-bit Direct interface • 8/16-bit Indirect interface • SPI (Mode 0, Mode 3) 2.3 Input Data Format • RGB 8:8:8, RGB 5:6:5, 8 bpp grayscale, or 8/16/24 bpp with Look-Up Table (LUT) 2.4 Display Interface • Active Matrix TFT...

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2.5 Display Features • Up to two display layers: • Main Layer • 8/16/24 bpp color depths with optional Look-up Table (LUT) • Independent rotation (0, 90, 180, 270° counter-clockwise) • PIP Layer • 8/16/24 bpp color depths with optional Look-up Table (LUT) • Independent rotation (0, 90, 180, 270° counter-clockwise) • Configurable PIP Effects allow automatic blink and fade in/out effects • Alpha Blending • Transparency • Look-up Tables for Main and PIP Layers (256 address x 24 bpp) 2.6 Miscellaneous • Single Clock Input: CLKI • Embedded PLL • Software initiated Power Save Modes • General...

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Chapter 3 Typical System Implementation Direct 16-bit Mode 1 Figure 3-1: Typical System Diagram (Direct 16-bit Mode 1, Panel Generic TFT 16-bit) Figure 3-2: Typical System Diagram (Direct 16-bit Mode 2, Generic TFT 18-bit) S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Figure 3-3: Typical System Diagram (Indirect 16-bit Mode 1, Generic TFT 16-bit) Figure 3-4: Typical System Diagram (Indirect 16-bit Mode 2, Generic TFT 18-bit) S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Figure 3-5: Typical System Diagram (Direct 8-bit, Generic TFT 16-bit) Figure 3-6: Typical System Diagram (Indirect 8-bit, Generic TFT 18-bit) S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Figure 3-7: Typical System Diagram (SPI, Generic TFT 24-bit) S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Chapter 4 Pins 4.1 Pinout Diagram IOVDD NC CLKI GND NC DB15 DB14 DB13 DB12 DB11 DB10 NC DB9 DB8 COREVDD GND NC DB7 DB6 DB5 DB4 NC DB3 DB2 NC DB1 IOVDD DB0 CS# WR# NC RD# PDT9 PDT8 PDT7 PDT6 GND NC PDT5 PDT4 PDT3 PDT2 NC PDT1 PDT0 IOVDD PCLK NC COREVDD GND DE HS VS PLLVDD VCP PLLGND NC NC Figure 4-1 S1D13L01 Pinout Diagram (QFP15-128pin) - Top View S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Input Output Bi-Directional (Input/Output) Power pin Analog Power pin Ground Analog Ground RESET# / Power Save State H = High level output L = Low level output Hi-Z = High Impedance Q = Output Pin, retains output state QB = IO Pin, if configured as output retains state Table 4-1: Cell Description Item H System LVCMOS Schmitt Input Buffer with Fail Safe H System LVCMOS Schmitt Input Buffer with pull-down resistor and Fail Safe H System LVCMOS Schmitt Input Buffer with pull-up resistor and Fail Safe H System LVCMOS Input Buffer with pull-down resistor and Fail Safe H System LVCOMOS Output...

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