Vol. 1: 6th Gen Intel® Processor for U/Y-Platforms
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6th Generation Intel® Processor Datasheet for U/Y-Platforms Volume 1 of 2 Supporting the Intel® Pentium® Processors and 6th Generation Intel® CoreTM Processors Families October 2015

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Revision History Initial release Revision Date October 2015

Introduction The 6th Generation Intel® Core™ processor family is a 64-bit, multi-core processor built on 14-nanometer process technology. The U-processor line and Y-processor line processors are offered in a 1-Chip Platform that includes the 6th Generation Intel® processor I/O Platform Controller Hub (PCH) die on the same package as the processor die. The processors are offered in a 2-Chip Platform and are connected to a discrete on the motherboard. See the following figure. Some of the processor SKUs are offered with On-Package Cache. The following table describes the different processor...

U-Processor Line and Y-Processor Line Platforms Digital Display Interface x 2 embedded DisplayPort* BIOS/FW Flash Fingerprint Sensor Touch Screen Gigabit Network Connection Accelometer Ambient Light Sensor

Supported Technologies • Intel® Virtualization Technology (Intel® VT) • Intel® Active Management Technology 11.0 (Intel® AMT 11.0) • Intel® Trusted Execution Technology (Intel® TXT) • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) • Intel® Hyper-Threading Technology (Intel® HT Technology) • Intel® 64 Architecture • Execute Disable Bit • Intel® Turbo Boost Technology 2.0 • Intel® Advanced Vector Extensions 2 (Intel® AVX2) • Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) • PCLMULQDQ (Perform Carry-Less Multiplication Quad word) Instruction • Intel® Secure Key •...

• DRAM Power Management and Initialization • Initialization Role of CKE • Conditional Self-Refresh • Dynamic Power Down • DRAM I/O Power Management • DDR Electrical Power Gating (EPG) • Power training Refer to Section 4.3 for more information. Processor Graphics Power Management Memory Power Savings Technologies • Intel® Rapid Memory Power Management (Intel® RMPM) • Intel® Smart 2D Display Technology (Intel® S2DDT) Display Power Savings Technologies • Intel® (Seamless & Static) Display Refresh Rate Switching (DRRS) with eDP port • Intel® Automatic Display Brightness • Smooth Brightness •...

• Intel® Turbo Boost Technology 2.0 Power Control Refer to Chapter 5, “Thermal Management” for more information. Package Support The processor is available in the following packages: • A 20 mm x 16.5 mm BGA package (BGA1515) for Y-processor line • A 42 mm x 24 mm BGA package (BGA1356) for U-processor line Processor Testability An XDP on-board connector is a must to enable the processor full debug capabilities. For the processor SKUs, a merged XDP connector is highly recommended to enable lower C-state debug. When separate XDP connectors will be used at C8–C10 states, the processor will need...

Terminology (Sheet 2 of 3) Term DDR4/DDR4-RS Description Fourth-Generation Double Data Rate SDRAM Memory Technology RS - Reduced Standby Power decision feedback equalizer Direct Memory Access Direct Media Interface Digital Thermal Sensor Error Correction Code - used to fix DDR transactions errors embedded DisplayPort* Execution Unit in the Processor Graphics Graphics in System Agent High-bandwidth Digital Content Protection High Definition Multimedia Interface Integrated Memory Controller 64-bit memory extensions to the IA-32 architecture Intel® DPST Intel Display Power Saving Technology...

Terminology (Sheet 3 of 3) Term Platform Power Architecture Guide (formerly PDDG) Platform Controller Hub. The chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security, and storage features. The PCH may also be referred as “chipset”. Platform Environment Control Interface Power Limit 1, Power Limit 2, Power Limit 3 The 64-bit multi-core component (package) Processor Core The term “processor core” refers to Si die itself, which can contain multiple execution cores. Each...

Related Documents Related Documents Document Document Number/Location Advanced Configuration and Power Interface 3.0 High Definition Multimedia Interface specification revision 1.4 Embedded DisplayPort* Specification revision 1.4 DisplayPort* Specification revision 1.2 PCI Express* Base Specification Revision 3.0 64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/products/processor/ manuals/index.htm

System Memory Interface • Two channels of DDR3L/-RS, LPDDR3 and DDR4/-RS memory with a maximum of two DIMMs per channel. DDR technologies, number of DIMMs per channel, number of ranks per channel are SKU dependent. • UDIMM, SODIMM, and Memory Down support (based on SKU) • Single-channel and dual-channel memory organization modes • Data burst length of eight for all memory organization modes • DDR3L/-RS I/O Voltage of 1.35V - based on processor line • LPDDR3 I/O voltage of 1.2V • DDR4/-RS I/O Voltage of 1.2V • 64-bit wide channels • /Non-ECC UDIMM and SODIMM DDR4/DDR3L/-RS support (based on...