Mobile 3rd Generation Intel® Core? Processor Family: Datasheet, Vol. 2
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Mobile 3rd Generation Intel® Core™ Processor Family, Mobile Intel® Pentium® Processor Family, and Mobile Intel® Celeron® Processor Family Datasheet – Volume 2 of 2

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Revision History Revision Number 001 002 Description Initial release • • Revision Date April 2012 Updated Section 2.6 to reflect support for Functions 0–2. Updated Section 2.7 to relfect support for Functions 0–2. ® Added Mobile Intel Pentium processor family support Added Mobile Intel® Celeron® processor family support Updated Section 2.6.49, “LCTL2—Link Control 2 Register” Added Section 2.10.45, RSTS—Root Status Register Added Section 2.10.46, DCAP2—Device Capabilities 2 Register Added Section 2.10.47, DCTL2—Device Control 2 Register Added Section 2.10.49, LCTL2—Link Control 2 Register...

Introduction This is Volume 2 of the Datasheet for the following products: • Mobile 3rd Generation Intel® Core™ processor family • Mobile Intel® Pentium® processor family • Mobile Intel® Celeron® processor family The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket. This document describes the configuration space registers or device-specific control and status registers (CSRs) only. This document does NOT include Model Specific Registers...

Processor Configuration Registers Processor Configuration Registers This chapter contains the following: • Register terminology • PCI Devices and Functions on processor • System address map • Processor register introduction • Detailed register bit descriptions Register Terminology Table 2-1 lists the register-related terminology and access attributes that are used in this document. Table 2-2 provides the attribute modifiers. Register Attributes and Terminology Item Read Only: These bits can only be read by software, writes have no effect. The value of the bits is determined by the hardware...

Processor Configuration Registers Register Attribute Modifiers Attribute Modifier Description Sticky: These bits are only re-initialized to their Reset Value by a "Power Good Reset". Note: Does not apply to RO (constant) bits. Key: These bits control the ability to write other bits (identified with a 'Lock' modifier) Lock: Hardware can make these bits "Read Only" using a separate configuration bit or other logic. Note: Mutually exclusive with 'Once' modifier. Once: After reset, these bits can only be written by software once, after which they become "Read Only". Firmware Write: The value of...

Processor Configuration Registers System Address Map The processor supports 512 GB (39 bit) of addressable memory space and 64 KB+3 of addressable I/O space. This section focuses on how the memory space is partitioned and the use of the separate memory regions. I/O address space has simpler mapping and is explained near the end of this section. The processor supports PEG port upper prefetchable base/limit registers. This allows the PEG unit to claim I/O accesses above 32 bit. Addressing of greater than 4 GB is allowed on either the DMI Interface or PCI Express* (PCIe*) interface. The...

Processor Configuration Registers • Device 6, Function 0: (PCIe x4 Controller) — MBASE/MLIMIT – PCI Express port non-prefetchable memory access window. — PMBASE/PMLIMIT – PCI Express port prefetchable memory access window. — PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access window — IOBASE/IOLIMIT – PCI Express port I/O access window. • Device 2, Function 0: (Integrated Graphics Device (IGD)) — IOBAR – I/O access window for internal graphics. Through this window address/data register pair, using I/O semantics, the IGD and internal graphics instruction port registers can...

Processor Configuration Registers Figure 2-1. System Address Range Example Host/System View Physical Memory (DRAM Controller View) TOUUD BASE Reclaim Limit - Reclaim BASE TOLUD BASE Legacy Address Range This area is divided into the following address regions: • 640-768 KB - Legacy Video Buffer Area • 768-896 KB in 16 KB sections (total of 8 sections) - Expansion Area • 896-960 KB in 16 KB sections (total of 4 sections) - Extended System BIOS Area • 960 KB-1 MB Memory - System BIOS Area

Processor Configuration Registers Figure 2-2. DOS Legacy Address Range OOOF FFFFh System BIOS (Upper) OOOE FFFFh Extended System BIOS (Lower) Expansion Area Legacy Video Area The DOS area is 640 KB (0000_0000h-0009_FFFFh) in size and is always mapped to the main memory controlled by the memory controller. 2.3.1.2 Legacy Video Area (A_OOOOh-B_FFFFh) The legacy 128 KB VGA memory range, frame buffer, (000A_0000h-000B_FFFFh) can be mapped to IGD (Device 2), to PCI Express (Device 1 or Device 6), and/or to the DMI Interface. The appropriate mapping depends on which devices are enabled and the...

Processor Configuration Registers Compatible SMRAM Address Range (A_0000h–B_FFFFh) When compatible SMM space is enabled, SMM-mode processor accesses to this range route to physical system DRAM at 000A_0000h–000B_FFFFh. PCI Express and DMI originated cycles to enable SMM space are not allowed and are considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCIe port. Monochrome Adapter (MDA) Range (B_0000h–B_7FFFh) Legacy support requires the ability to have a second graphics...