MM4050A6-6G
17Pages

MM4050A6-6G User Manual 1.Specifications Model Graphics Processing Unit NVIDIA GeForce RTX4050 Max-Q Graphics Clock Memory Size Memory Clock Memory Bandwidth Display Features Number of output Channel Board Power Board Dimensions MXM Graphics Module Version 3.1 Type A (70x82mm) Operation System Operating Temperature Storage Temperature Operating Humidity Storage Humidity Render Config Shader Processing Units Tensor Core

MM4050A6-6G User Manual Theoretical Peformance Pixel Rate Texture Rate Graphics Features DirectX Shader Model Video Playback *Total resolution based on every display resolution is 1920*1080@60Hz.

GDDR6 x32 Memory down GDDR6 x32 Memory down GDDR6 x32 Memory down GDDR6 x32 Memory down GDDR6 x32 Memory down GDDR6 x32 Memory down IPFB IFPC Power Management (PWR_EN, PWR_GOOD)

MM4050A6-6G User Manual 3.MXM Board Outlines Figure 3.1 shows the board outlines (top side view) for Type A MXM modules. An additional system keep-out of 0.5mm [0.020] per side is allowed on the PCB to accommodate whatever means of production panelization is required. This additional clearance is above and beyond the dimensional limits presented here. The location of these features is not specified or controlled. Figure 3.1 Board Outlines Table 3.1 Board Outline Dimensions Symbol

MM4050A6-6G User Manual Figure 3.2 Board Slots Detail Table 3.2 Board Slots Dimensions Symbol

MM4050A6-6G User Manual 4.MXM PCB Mounting Holes All MXM version 3.1 modules have 6 holes. Two are used to secure the board to the system and the other four to fasten the thermal solution to the module. Figure 4.1 Mounting Holes Table 4.1 Mounting Holes Dimensions Symbol

MM4050A6-6G User Manual 5.Connector Pinout Table 5.1 and Table 5.2 list the connector pinout. Table 5.1 Connector Pinout Pin Signal Name Signal Name Signal Name Signal Name

MM4050A6-6G User Manual Table 5.2 Connector Pinout(continued) Pin Signal Name Signal Name Signal Name Signal Name PEX_CLK_REQ # PEX_RST# VGA_DDC_DA T VGA_DDC_CL K

MM4050A6-6G User Manual 6.MXM Connector Figure 6.1 MXM Connector (Card Top) Figure 6.2 MXM Connector (Card Bottom) 7.Power Group Table 7.1 shows the MXM module power requirements. The voltage tolerances in the table are specified as measured on module edge finger. The system must be able to supply the full specified current on rails (except PWR_SRC) at all times. Th current capability of the PWR_SRC rail must be defined by the system in the MXM system information structure. Table 7.1 MXM Power Rails Signal Name Note: PWR_SRC voltage range is assumed to be DC or RMS. However under any...

MM4050A6-6G User Manual 8.Power Sequencing There is no power sequencing requirement for the input voltages to the MXM module. However the PWR_EN signal may be asserted only after all power rails are within specified tolerance. The state of PWR_GOOD is undefined until all rails are fully ramped. Refer to Figure 8.1 for details Figure 8.1 Power Sequencing 9.Module Power Down and Power Up The MXM module may be powered down using the PWR_EN signal. The system designer may choose to shut down or keep the input power while the module is powered down. Refer to Figure 9.1 for details. Figure 9.1...

MM4050A6-6G User Manual 10.Reset Requirements System reset may be deasserted only after the assertion of the PWR_GOOD signal. Figure 10.1 shows the reset requirements relative to the PWR_EN and PWR_GOOD signals. This sequence must be followed on initial power on, system reset and resume from suspend/hibernate. Figure 10.1 Reset Sequencing 11.DisplayPort Interface DC blocking capacitors of DisplayPort must be placed on the system board. In addition to the MXM implementation of Dual-mode DisplayPort requires the circuit in Figure 11.1 on the AUX lines for proper dongle detection. The HPD...

MM4050A6-6G User Manual 12.DVI/HDMI on DP Interface Native DVI or HDMI connector support can be implemented using a DisplayPort interface. Additional circuitry is required on the system and the proper signal mapping must be observed. As Figure 12.1 shows, 499Ω 1% pull-down resistors to ground on the DP lane signals must be placed on the con1ector side of AC coupling capacitors gated by a FET to limit the leakage. Additionally level shifting circuits must also be implemented on DDC Data and Clock. Table 12.1 shows the mapping to connect the signals from the MXM connector to the HDMI/DVI...

Cooling Suggestion: 1、显卡建议先固定在散热器上，散热器外径为 4mm，M2 的螺柱。 2、散热器的重量要用箱体来支撑固定。 3、显存和 MOS 要加导热垫。 Components

MM4050A6-6G User Manual 15.Performance Benchmark Single-Precision FLOPS(CUDA-Z) Double-Precision FLOPS(CUDA-Z) 16.Driver Windows 11：https://pan.baidu.com/s/1uFnoXduKJ77AlPj7kvFtQQ?pwd=rv3y Windows 10 64bit：https://pan.baidu.com/s/1uFnoXduKJ77AlPj7kvFtQQ?pwd=rv3y Linux 64bit: Linux x64 (AMD64/EM64T) Display Driver | 550.78 | Linux 64-bit | NVIDIA Uninstall Driver Video： https://www.douyin.com/user/MS4wLjABAAAAfV567McP9KjHrjFWngJgFG8h7XMSWsqH55hBIryutmg? modal_id=7321980490926

2、确认 PCIE 复位信号。 3、主板 BIOS 更改为 UEFI BIOS。 Windows 10： （需 1809 版本之后） 在主板 BIOS 下，将 CSM 中 CSM Support 设置由 Enabled 更改为 Disabled。 1、原系统显卡驱动删除干净。（请使用 Display Driver Uninstaller 删 除，https://www.wagna

将 xorg.conf 文件内容清空。 检查 PCIE LANE Numbering Reversal 设置。 主要关注下上电和 pcie，确认下 1、PCIE 的连接（是否 0-15 反、差分正负反、x16 是否拆分，bios 可修 改，软硬件要一致） ，耦合电容