NXP i.MX 8M NanoTM - based System-on-Module

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Document Revision History Revision 1.00 Notes Official Release Updated SOM power requirements Table: 55 see Important Note Updated power consumption Table: 56 updated Add power up timing diagram – see section 8.22.3.18.22.3.1 Add SOM_3V3_PER loading requirement note – see “Table 51: Power Pins“ Added Audio Codec note about RC network – see 8.9.1 Update pins 83&85 for usage of UART4 as Symphony Base board debug UART (old pins 54&56) Updated Table 1 eMMC ordering notation Update power consumption Table 56. Updated Table 1 – delete temperature figures CAN-FD changes for SOM version V1.3 and onward:...

Overview 4.1. General Information The VAR-SOM-MX8M-NANO offers cost-effective integration and affordable performance for smart, connected, power-efficient devices requiring graphics, vision, voice control, intelligent sensing and general-purpose processing. It perfectly fits various embedded products, the growing market of connected and portable devices and segment for connected streaming audio/video devices, scanning/imaging devices and various devices requiring high-performance, low-power processors. The product is based on the NXP i.MX 8M family of multi-purpose processors, featuring a quad...

NXP i.MX 8M NANO series SOC o i.MX 8M NANO family ARM® Cortex™-A53 Core up to 1.5GHz quad core o 750MHz ARM® Cortex™-M7 o Up to 2GB DDR4 RAM o Up to 8-bit 64GB eMMC or up to 512MB 8-bit NAND flash for boot and storage Display Support o Dual channel LVDS display interface o MIPI DSI Networking o 10/100/1000 Mbit/s Ethernet Interface o Certified dual band Wi-Fi 802.11 ac/a/b/g/n or single band 802.11 b/g/n Bluetooth: 5.2/BLE o CAN-FD Camera o MIPI-CSI – CMOS Serial camera Interface 4 lanes Audio o Analog Stereo line in o Analog headphones out o Digital microphone o 6x Digital audio (SAI, SPDIF,...

4Kb I2C EEPROM (Internal Use Only) DSI-LVDS Bridge ENET RGMII Ethernet PHY Ethernet/RGMII NVCC_ENET Audio CODEC Buffer + Level Shift WiFi + BT Single/Dual Band Digital Audio Pin2pin with additional VAR-SOM products. Please check pin-list document for details Figure 1 : VAR-SOM-MX8M-NANO Block Diagram VAR-SOM-MX8M-NANO_V1.x Datasheet Page 9

Main Hardware Components This section summarizes the main hardware building blocks of the VAR-SOM-MX8M-NANO. 5.1. NXP i.MX 8M NANO Overview The i.MX 8M Nano is focused on delivering an excellent media and machine learning experience, combining capabilities with high-performance processing optimized for lowpower consumption. The i.MX 8M Nano Media Applications Processor is built to achieve both high performance and low power consumption and rely on a powerful, fully coherent core complex based on a quad Cortex-A53 cluster, Cortex-M7 low-power coprocessor, and graphics accelerator. The i.MX 8M...

The i.MX 8M Family Applications Processors are based on the Arm Cortex-A53 MPCore™ Platform, which has the following features: o Quad symmetric Cortex-A53 processors, including: ▪ 32 KB L1 Instruction Cache ▪ 32 KB L1 Data Cache ▪ Media Processing Engine (MPE) with NEON technology supporting the Advanced Single Instruction Multiple Data architecture o Floating Point Unit (FPU) with support of the VFPv4-D16 architecture o Support of 64-bit Armv8-A architecture o 512 KB unified L2 cache o Target frequency of 1.5GHz for Commercial and 1.4Ghz for Industrial. Arm Cortex-M7 Platform The Cortex-M7 Core...

Interrupts and DMA Interrupts and DMA include: • 128 shared peripheral interrupts routed to Cortex-A53 Global Interrupt Controller (GIC) and Cortex-M7 nested vector interrupt controller (NVIC) for flexible interrupt handling • Three Smart direct memory access (SDMA) engines. Although these three engines are identical to each other, they are integrated into the processor to serve different peripherals. o SDMA-1 is a general-purpose DMA engine which can be used by low speed peripherals including UART, SPI and also others peripherals. o SDMA-2 and SMDA-3 is used for audio interface, including SAI-2/3/5/6/7,...

Graphics Processing Unit (GPU) The chip incorporates the following Graphics Processing Unit (GPU) features: • • • • • 2D/3D acceleration 2 shader Supports OpenGL ES 1.1, 2.0, 3.0 Supports OpenCL Supports Vulkan Display/Camera Interfaces The chip has the following display support: • LCDIF Display Controller: o Supports up to 2 layers of overlay o Support up to 1080p60 display through MIPI DSI MIPI Interface: o 4-lane MIPI CSI interface o 4-lane MIPI DSI interface o Supports 4 cameras using MIPI-CSI2 Virtual Channel support (ISI module) ISI (Image Sensor Interface): o The ISI is a simple camera...

General Connectivity Interfaces The chip contains a rich set of general connectivity interfaces, including: • One USB 2.0 OTG controller with integrated PHY interface o Spread spectrum clock support • Three Ultra Secure Digital Host Controller (uSDHC) interfaces o MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec o SD/SDIO 3.01 compliance with 200 MHZ SDR signaling to support up to 100 MB/sec o Support for SDXC (extended capacity) • One Gigabit Ethernet controller with support for EEE, Ethernet AVB and IEEE1588 • Four universal asynchronous receiver/transmitter (UART) modules...

General-purpose input/output (GPIO) modules with interrupt capability Input/output multiplexing controller (IOMUXC) to provide centralized pad control Power Management The power management unit consists of: • Temperature sensor with programmable trip points • Flexible power domain partitioning with internal power switches to support efficient power management System Debug The system debug features are: • ARM CoreSight debug and trace architecture • Trace Port Interface Unit (TPIU) to support off-chip real-time trace • Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering...