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Document Revision History Revision 1.0 Notes Initial - Preliminary Pre-launch editing changes - Preliminary Pre-launch changes Describes layout change for V1.1: Pinout changes on J1: 23,25,29,31,72 Pin function changes on J1.15, J3: 32,69 See sections: 5.3; 6.4.3; 6.7.3; 6.15.1; 6.18.3; 6.19.1 - Preliminary Official product release Image update Describes layout change for V1.2: Pinout changes on J1.31 (Table17; Section 7.4) Correct section 6.9 links Section 6.18.3 Table 58 – added clarifications (General System control) Section 6.4 Update. Remove J1.72 function as CONN_WIFI_DISN Section 7.3:...

DART-MX8M_V1.x Data Sheet Page, 4

DART-MX8M_V1.x Data Sheet Page, 5

DART-MX8M_V1.x Data Sheet Page, 6

Overview 3.1. General Information The DART-MX 8M offers high-performance processing for a low-power System-on-Module. It perfectly fits various embedded products, the growing market of connected and portable devices and segment for connected streaming audio/video devices, scanning/imaging devices and various devices requiring high-performance, low-power processors. The product is based on the NXP i.MX 8M Dual/Quad Lite/Quad family of multi-purpose processors, featuring an ARM® Cortex™-A53 up to 1.5GHz with an additional 266MHz ARM Cortex-M4 core. This heterogeneous multicore processing architecture...

NXP i.MX 8M series SOC o i.MX 8M Dual/Quad Lite/Quad ARM® Cortex™-A53 Core 1.5GHz o 266MHz ARM® Cortex™-M4 o Up to 4GB LPDDR4 RAM o 8-bit up to 64GB eMMC boot and storage Display Support o Dual channel LVDS display interface o HDMI/eDP/DP o MIPI DSI Networking o 10/100/1000 Mbit/s Ethernet Interface o Certified Wi-Fi 802.11 ac/a/b/g/n o Bluetooth: 5.2/BLE Camera o 2 x CSI – CMOS Serial camera Interface 4 lanes each Audio o Analog Stereo line in o Analog headphones out o Digital microphone o 6x Digital audio (SAI, SPDIF) USB o 2 x USB 3.0/2.0 OTG Other Interfaces o SDIO/MMC o 2 x PCIe v2.0 o Serial...

PMIC eMMC 4Kb I2C EEPROM (Internal Use Only) SNVS LVDS DUAL CH DSI-LVDS Bridge MIPI DSI/ LVDS DUAL CH DISP Ethernet / RGMII Audio CODEC uSDHC Buffer + Level Shift Figure 1 : DART-MX8M Block Diagram DART-MX8M_V1.x Data Sheet Page, 9

Main Hardware Components This section summarizes the main hardware building blocks of the DART-MX8M. The i.MX 8M Dual/8M QuadLite/8M Quad Applications Processors are the first products of the growing i.MX 8M family targeting the consumer market. They achieve both high performance and low power consumption and rely on a powerful, fully-coherent core complex based on a quad Cortex-A53 cluster, with graphics processing GPU supporting the latest graphic APIs. The i.MX 8M family provides additional computing resources and peripherals: • Advanced security modules for secure boot, cipher acceleration...

The i.MX 8M family Applications Processors are based on the ARM Cortex-A53 MPCore™ platform, which has the following features: • Quad symmetric Cortex-A53 processors, including: o 32KB L1 Instruction Cache o 32KB L1 Data Cache o Media Processing Engine (MPE) with NEON technology supporting the Advanced Single Instruction Multiple Data (SIMD) architecture o Floating Point Unit (FPU) with support of the VFPv4-D16 architecture • Support of 64-bit ARMv8-A architecture • 1 MB unified L2 cache • Target frequency of 1.5GHz Cortex-M4 core platform includes the following: • Low power microcontroller available...

Interrupts and DMA include: • 128 shared peripheral interrupts routed to Cortex-A53 Global Interrupt Controller (GIC) and Cortex-M4 nested vector interrupt controller (NVIC) for flexible interrupt handling • Two Smart direct memory access (SDMA) engines. Although these two engines are identical to each other, they are integrated into the processor to serve different peripherals. Each SDMA controller supports 48 DMA requests. On-Chip Memory The on-chip memory system consists of the following: • Boot ROM (96KB) • On-chip RAM (128KB + 32KB) External Memory Interface The external memory interfaces...

Video Processing Unit (VPU) The chip incorporates the following Video Processing Unit (VPU) features: • 4Kp60 HEVC/H.265 Main, Main10 (Hantro G2) with best effort for 4Kp75 • 4Kp75 is needed to support PiP (Picture in Picture) for live TV and dual layer Dolby Vision decoding one 4Kp60 stream and one 1080p60 stream • 4Kp60 VP9 Profile 0, 2 (10 bit) (Hantro G2) • 4Kp30 AVC/H.264 Baseline, Main, High decoder (Hantro G1) • 1080p60 MPEG-2, MPEG-4p2, VC-1, VP8, RV9, AVS, MJPEG, H.263 decoder (Hantro G1) • Frame Buffer Compression – Lossless compression of buffers • TrustZone support Display Interfaces...

General Connectivity Interfaces The chip contains a rich set of general connectivity interfaces, including: • Two PCI Express (PCIe): o Single lane supporting PCIe Gen 2 o Dual mode operation to function as root complex or endpoint o Integrated PHY interface o Supports L1substate • Two USB 3.0/2.0 OTG controller with integrated PHY interface • Spread spectrum clock support • Two Ultra Secure Digital Host Controller (uSDHC) interfaces • MMC 5.0 compliance with HS400 DDR signaling to support up to 400 MB/sec • SD/SDIO 3.01 compliance with 200 MHZ SDR signaling to support up to 100MB/sec • Support...

Multicore Support Multicore support contains: • Resource domain controller (RDC) to support isolation and safe sharing of system resources • Messaging unit (MU) • Hardware Semaphore (SEMA42) • Shared bus topology General-purpose input/output (GPIO) modules with interrupt capability Input/output multiplexing controller (IOMUXC) to provide centralized pad control Power Management The power management unit consists of: • Temperature sensor with programmable trip points • Flexible power domain partitioning with internal power switches to support efficient power management System Debug The system...