VARISCITE LTD. DART-MX8M-PLUS V1.x Datasheet NXP i.MX 8M PLUSTM - based System-on-Module
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NXP i.MX 8M PLUSTM - based System-on-Module

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1. Document Revision History Revision 1.0 1.01 Notes Initial - Preliminary -Correct Table 1 Hardware Configuration Options “LD” to “DSCM” configuration (DSI export locations) -Update all related tables for “DSCM” configuration -Removed note for CAN Bus availability on Industrial grade only. NVCC_3V3 output power supply capabilities section added Added Section 8.21.1.1 for NVCC_SAI1_SAI5 Updated notes for pin referenced to NVCC_SAI1_SAI5 Updated Reliability data section 10 Updated Mechanical drawing section 11.3 Updated ECSPI Features list section 8.13 Updated Sections 5.1.4, 5.1.8-9,...

4. Overview General Information The DART-MX8M-PLUS offers a high-performance processing for a low-power System-on-Module. The product is based on the i.MX 8M Plus family which is a set of NXP products focused on machine learning applications, combining state-of-art multimedia features with high-performance processing optimized for low-power consumption. The i.MX 8M Plus Media Applications Processor is built to achieve both high performance and low power consumption and rely on a powerful, fully coherent core complex based on a quad Cortex-A53 cluster and Cortex-M7 low-power coprocessor,...

Feature Summary • NXP i.MX8M-PLUS series SOC o 4x Cortex A53 up to @ 1.8 GHz o 1x Cortex M7 @ 800 MHz o 1x Hi-Fi DSP @ 800 MHz GPU and the AI/ML accelerators specs o Neural Processing Unit (NPU): Delivers up to 2.3 TOPS Memory o Up to 8GB LPDDR4 RAM @ 2000Mhz o 8-bit up to 64GB eMMC boot and storage Display Support o 2x LVDS interface 4-lane each o HDMI 2.0a o 1x MIPI DSI with up to 4 data lanes Networking o 2x 10/100/1000 Mbit/s Ethernet Interface o Certified Wi-Fi 802.11 ac/a/b/g/n o Bluetooth: 5.2/BLE Camera o Up to 2x MIPI CSI – CMOS Serial camera Interface 4 lanes o 375 Mpixel/s HDR...

Block Diagram Figure 1 : DART-MX8M-PLUS Block Diagram

5. Main Hardware Components This section summarizes the main hardware building blocks of the DART-MX8M-PLUS. NXP i.MX 8M Plus Overview The i.MX 8M Plus family focuses on machine learning and vision, advanced multimedia, and industrial IoT with high reliability. It is built to meet the needs of Smart Home, Building, City and Industry 4.0 applications. • Powerful quad or dual Arm® Cortex®-A53 processor with a Neural Processing Unit (NPU) operating at up to 2.3 TOPS. Real-time control with Cortex-M7. Robust control networks supported by dual CAN FD (IT version) and dual Gigabit Ethernet, one...

i.MX 8M Plus Block Diagram Figure 2 : i.MX 8M Plus Block Diagram

ARM Cortex-A53 MPCore™ Platform The i.MX 8M Plus family Applications Processors are based on the ARM Cortex-A53 MPCore™ platform, which has the following features: • Quad symmetric Cortex-A53 processors operation up to 1.8 GHz, including: o 32 KB L1 Instruction Cache o 32 KB L1 Data Cache o Media Processing Engine (MPE) with NEON technology supporting the Advanced Single Instruction Multiple Data architecture o Floating Point Unit (FPU) with support of the VFPv4-D16 architecture Support of 64-bit Armv8-A architecture 512 KB unified L2 cache Arm Cortex M7 Platform The Cortex-M7 Core Platform...

Interrupts and DMA Interrupts and DMA include: • • • 160 shared peripheral interrupts routed to Cortex-A53 Global Interrupt Controller GIC) and Cortex-M7 nested vector interrupt controller (NVIC) for flexible interrupt handling Three Smart direct memory access (SDMA) engines. Although these three engines are identical to each other, they are integrated into the processor to serve different peripherals. o SDMA-1 is a general-purpose DMA engine which can be used by low speed peripherals including UART, SPI and also other peripherals. o SDMA-2 and SMDA-3 is used for audio interface, including...

Graphics Processing Unit (GPU) The chip incorporates the following Graphics Processing Unit (GPU) features: • One GPU for 2D and composition acceleration o o o Supports multi-source composition Supports one-pass filter Supports tile format Two Shader Execution Units Supports OpenGL ES 1.1, 2.0, 3.0, 3.1 Supports OpenCL 3.0 Supports OpenVG 1.1 Supports OpenGL 4.0 Supports EGL 1.5 Supports Vulkan 1.1 Supports tile format Graphics Processing Unit (VPU) The chip incorporates the following Video Processing Unit (VPU) features: • Video Decode: o 1080p60 HEVC/H.265 Main, Main 10 (up to level 5.1)...

Display Interfaces The chip has the following display support: • Three LCDIF Display Controllers: o One LCDIF drives MIPI DSI o One LCDIF drives LVDS Tx o One LCDIF drives HDMI Tx o Support up to 1920x1200p60 display per LCDIF if no more than 2 instances used simultaneously, or 2x 1080p60 + 1x 4kp30 on HDMI if all 3 instances used simultaneously. o Supports 8-bit / 16-bit / 18-bit / 24-bit / 32-bit pixel depth o Supports one layer MIPI Interface: o One 4-lane MIPI DSI interface o Two 4-lane MIPI CSI interfaces Two 4-lane LVDS interfaces ISI (Image Sensor Interface): o The ISI is a simple...

General Connectivity Interfaces The chip contains a rich set of general connectivity interfaces, including: • One PCI Express (PCIe): o Single lane supporting PCIe Gen 3 o Dual mode operation to function as root complex or endpoint o Integrated PHY interface o Supports L1 low power substate Two USB 3.0 Type C controllers with integrated PHY interface o Backwards compatibility with USB 2.0 o Spread spectrum clock support Three Ultra Secure Digital Host Controller (uSDHC) interfaces o MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec o SD/SDIO 3.01 compliance with 200...