Application Note: Spartan-3E and Virtex-5 FPGAs Configuring Xilinx FPGAs with SPI Serial Flash XAPP951 (v1.3) September 23, 2010 Author: Stephanie Tapp This application note discusses the Serial Peripheral Interface (SPI) configuration mode introduced in the Virtex®-5 and Spartan®-3E FPGA families. The required connections to configure the FPGA from an SPI serial flash device are discussed and the configuration flow for the SPI mode is shown. Special precautions for configuring from an SPI serial flash are given, and the ISE® Design Suite iMPACT direct SPI programming solution is described. Note: The ISE Suite iMPACT tool version 11.4 is the last supported release for direct in-system SPI programming and is captured in this application note. For new designs, the iMPACT indirect in-system SPI programming solution is recommended. This solution uses a single JTAG connection to both configure the FPGA and indirectly program the flash. For additional information see Introduction to Indirect Programming — SPI or BPI Flash Memory in the iMPACT Help at http://www.xilinx.com/support/ documentation/sw_manuals/xilinx11/isehelp_start.htm. The principles described in this application note apply to the external SPI flash configuration mode of the Extended Spartan-3A family with few differences. See UG332, Spartan-3 Generation Configuration User Guide for the unique details and requirements of the Extended Spartan-3A family's SPI configuration mode. Xilinx FPGAs are CMOS configurable latch (CCL) based and must be configured at power-up. Traditionally, Xilinx FPGA configuration is accomplished via the IEEE Std 1149.1 (JTAG) interface, a microprocessor, or the Xilinx PROMs (Platform Flash PROMs). In addition to these traditional methods, a direct configuration interface to SPI serial flash is now available. The direct configuration interface for SPI serial flash memories in the Virtex-5 and Spartan-3E FPGAs broadens the available configuration solutions for Xilinx designers and is the focus of this application note. SPI serial flash memories are popular because they can be easily accessed post-configuration, offering random-access, non-volatile data storage to the FPGA. Systems with SPI serial flash memory already onboard can also benefit from having the option to configure the FPGA from the same memory device. The SPI protocol does have a few variations among vendors. Variations among some vendors are highlighted along with the connections required between the FPGA and SPI serial flash memory for configuration. The ISE software tools for SPI-formatted PROM file creation and programming during prototyping for select vendors are shown. SPI serial flash memories are not supplied by Xilinx and must be purchased from third-party vendors such as Numonyx. SPI serial flash memories use the Serial Peripheral Interface (SPI), a four-wire, synchronous serial data bus. This serial data link was pioneered as a serial communication interface between a microcontroller and its peripherals and is a popular interface in embedded and consumer markets. This interface can now also be used to configure Xilinx FPGAs. An SPI system typically consists of a master device and a slave device (Figure 1). When using this four-signal interface to configure a Xilinx FPGA from an SPI serial flash, the FPGA is the master device and the SPI serial flash is the slave device. © Copyright 2006–2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

X-Ref Target - Figure 1 Xilinx FPGA SCK MOSI Master Device SPI Serial Flash Slave Device Basic Block Diagram for SPI Configuration Mode The master FPGA device controls the timing via the SCK clock signal. Data is clocked out of the FPGA master and into the SPI serial flash slave on the MOSI signal after the select signal SS goes Low. During the same clock cycle, data is clocked out of the SPI serial flash slave and into the FPGA master using the MISO signal. Data is clocked out of each device on one edge and clocked into each device on the next opposite edge in the period. In addition to the...

Configuring FPGAs from SPI Serial Flash Configuring FPGAs from SPI Serial Flash Spartan-3E and Virtex-5 FPGAs can be configured from a single SPI serial flash memory. The typical configuration density requirements for these FPGAs are provided in Table 2. Table 2: Typical Configuration Bit Requirements Configuration Bits (Per Device) Smallest SPI Serial Flash Required A larger SPI serial flash device can be used for daisy-chained applications, storing multiple FPGA configuration bitstreams, or for applications storing additional user data, such as code for the embedded MicroBlaze™ or PowerPC™...

Configuring FPGAs from SPI Serial Flash A detailed SPI configuration setup is shown in Figure 2, page 5, where the Virtex-5 FPGA is the master and the Numonyx SPI serial flash is the slave. The configuration connections from the SPI serial flash to the FPGA are highlighted in this diagram. For information on the programming and configuration headers used by the Xilinx cables, refer to Hardware and Connections for SPI Programming. A detailed SPI configuration setup is shown in Figure 3, page 6, where the Spartan-3E FPGA is the master and the Numonyx SPI serial flash is the slave. The configuration...

Configuring FPGAs from SPI Serial Flash X-Ref Target - Figure 2 Ribbon Cable Header for FPGA JTAG Configuration Ribbon Cable Header for SPI Direct Programming(6) INIT_B DONE SPI Variant ‘1’ ‘0’ Select (Read 0X03) '1' VCCO_2 supplies the SPI configuration dual-mode pins: MOSI, FCS_B, and FS[2:0] VCC_CONFIG (Vcco_0) is the configuration output supply voltage and supplies the dedicated configuration pins: TMS, TCK, TDO, TDI, M[2:0], HSWAPEN, PROG_B, DONE, INIT_B, CCLK, D_IN. PROG_B should be held Low during the direct programming of the SPI serial flash. PROG_B can be driven Low to High with external...