MPEG-4 CODEC
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MPEG-4 Audiovisual Codec LSI Preliminary TC35273 TOSHIBA Confidential 2000-4-27 1/23 Version 0.90 TOSHIBA MPEG-4 Audiovisual LSI TC35273 Tentative Technical Data Sheet MPEG-4 Audiovisual LSI Features TC35273 is an MPEG-4 audiovisual codec LSI which supports 3GPP 3G-324M video telephony system. MPEG-4 video codec with QCIF (176x144 pixel) at 15 frames/s, AMR (Adaptive Multi Rate) speech codec, and ITU-T H.223 are executed concurrently at around 70MHz clock rate. Three signal processing units, an MPEG-4 video codec, a speech codec / audio decoder, and a multiplex / demultiplex unit, are integrated on a single chip. A 12-Mbit embedded DRAM is integrated as a shared memory for the three signal processing units. The embedded DRAM helps to reduce power consumption without performance degradation. Each signal processing unit consists of a 16-bit RISC processor and dedicated hardware accelerators so as to bring programmability, high performance and low power consumption. Firmware programs for the RISCs are downloaded into the embedded DRAM before starting operation. Various applications are performed by choosing an appropriate firmware. General host interface are adopted in order to support various host CPU. 2.5x to 6x of PLL is integrated on the chip for easy system integration. • TOSHIBA continually is working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. • The products described in this document are subject to foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. P-FBGA201-1515-0.80A5

MPEG-4 Audiovisual Codec LSI Preliminary TC35273 TOSHIBA Confidential 2000-4-27 2/23 Version 0.90 • The circuit contained herein is presented only as a guide for the applications, and it is not guaranteed.

MPEG-4 Audiovisual Codec LSI Preliminary TC35273 TOSHIBA Confidential 2000-4-27 3/23 Version 0.90 1. Functional Specifications 1.1 MPEG-4 Video Codec ISO MPEG-4 International Standard Simple Profile @Level 1 is supported. Encoding and decoding with QCIF (176 x 144 pixel) at 15 frames per second are executed. YCbCr 4:2:2 8bit digital camera input. A CMOS camera or an NTSC decoder is connected. Temporal filter and size conversion for pre-filter function. YCbCr 4:2:2 8bit digital display output. An NTSC encoder or an LCD controller is connected. Size conversion and de-blocking filter for...

MPEG-4 Audiovisual Codec LSI Preliminary TC35273 TOSHIBA Confidential 2000-4-27 4/23 Version 0.90 1.2. System configuration. Fig. 1 illustrates a block diagram of this LSI. Three signal processing core, peripheral interfaces, and 12-Mbit DRAM are integrated in a single chip. Bitstream input/output are performed via a network interface in the Mux/Demux core. A Microphone and a speaker can be connected to a PCM interface in a speech/audio core via external DAC and ADC. TOSHIBA CMOS camera is connected to a camera interface via a camera DSP “TC90A50F” or “TC90A70F”. NTSC camera is also...

MPEG-4 Audiovisual Codec LSI Preliminary TC35273 TOSHIBA Confidential 2000-4-27 5/23 Version 0.90 2. Terminals 2.1 Pin Assignment TBD 2.2 Pin Allocation TBD 2.3 I/O Pins Fig. 2 Pin Map TC35273 MPEG-4 Audiovisual LSI PLLDIV PLLFN PLLAVD PLLBP PLLAVS 3 /RESET /HCS /HWR HADDR /HRD HDAT /HWAIT 7 16 /HACK HINT TREOUT TEST0-3 NWCLK /NWOEN NWDO /NWIEN NWDI NWIFS NWOFS VGSADIO VGSBDO VGSCLK CAMCLK CAMHREF CAMVREF CAMFSEL CAMPIXEL DISPCLK DISPHSYNC DISPYSYNC DISPBLK DISPPIXEL ADIMCLK ADOMCLK ADLRCLK ADSCLK ADSDO ADSDI ADCMD PLL Pins Host Interface Test Pins Network Interface Camera Interface Video...

MPEG-4 Audiovisual Codec LSI Preliminary TC35273 TOSHIBA Confidential 2000-4-27 6/23 Version 0.90 Table 1. System Control Signals Signal Name In/Out Bit Width Description /RESET In 1 System Reset Input (Low Active). When the LSI is reset, the reset pin has to be low for more than 16 clock cycles. When power on, the LSI has to be reset after PLL locked. It takes approximately 100us until the PLL locked. STANDBY In 1 System Standby Input (High Active). When it is high, power is not supplied to the internal logic, SRAM, and DRAM. “0”: Normal Operation. “1”: Standby. Table 2. PLL Control...

MPEG-4 Audiovisual Codec LSI Preliminary TC35273 TOSHIBA Confidential 2000-4-27 7/23 Version 0.90

MPEG-4 Audiovisual Codec LSI Preliminary TC35273 TOSHIBA Confidential 2000-4-27 8/23 Version 0.90 Table 5 Video Camera Interface Signal Name In/Out Bit Width Description CAMCLK In 1 Clock signal from camera. CAMHREF In 1 HREF signal from camera. CAMVREF In 1 VREF signal from camera. CAMFSEL In 1 Field select signal from camera in an NTSC mode. CAMPIXEL In 8 Luminance and chrominance data from camera. Table 6 Video Display Interface Signal Name In/Out Bit Width Description DISPCLK In 1 Clock signal from display. /DISPHSYNC In 1 HSYNC signal from display. /DISPVSYNC In 1 VSYNC signal form...