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SGS-THOMSON ST7282

SGS-THOMSON ST7282
23Pages

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ST7282A5 - ST7282B5 ROM FROM EPROM PRELIMINARY DATASHEET s s 24 digital I/O (ST7 IO3) with pull up, interrupt input, analog input, push-pull/ open drain output 36 LCD/IO combi pins (ST7 LCIO1) with pull-up, interrupt input, push-pull, open drain output, LCD output Group & Block Sync Module for RDS (ST7 RDS GB)

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Figure 1. Block Diagram

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1.1 Quick Reference The ST7282A5/B5 is a 32K ROM version of the ST72 family, using the ST72CORE and N-Well technology. It is derived from EPROM M4 version replacing EPROM by ROM. Two different commercial products are supported by this device : ST7282A5 (no LCD driver) functionnality described in specification SD70KL1618 ed. F) and ST7282B5 (LCD driver) functionnality described in specification 96096 ed. B). It contains an LCD controller/driver with 20 segment and 16 backplane outputs able to drive up to 20 x 16 = 320 segments. The LCD control logic reads automatically data from the LCD-RAM...

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1.2.3 Electrical Characteristics The values given in the specifications of dedicated functions are generally not applicable for chips. Therefore, only the limits listed below are valid for the product. T = -40 ... +85°C, VDD - VSS = 5V unless otherwise specified. PARAMETER Supply voltage Supply current Run Mode Supply current Wait Mode Supply current slow wait mode Supply current halt mode Supply current Reset Mode f=8.55MHz Display voltage Supply voltage differences (VDD, VDDP, VDDA) (VSS, VSSP, VSSA) OSCILLATOR: Input/output cap Cin, Cout Oscillation frequency Built up time 2) Input...

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I/O PORTS: Input leakage current 7) Input leakage current Input voltage high leading edge trailing edge Output voltage high Output voltage high Output voltage slope Output current slope Noise amplitude Pullup Resistor Current Total Error tcon Conversion time Analog source impedance Osc. frequency range LCD DRIVER: Frame frequency COM output voltage high SEG output voltage high EEPROM: Write time 1)Operation below 30 KHz Mis possible but requires increased supply current 2)Time to build up the oscillation amplitude to 90% VDD 3)Pull-up resistor 4)WD not active 5)WD generating a reset...

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8) noise at VDD, VSS < 10 mV 9)The DC offset voltage refers to all segment and common outputs. It is the difference between the measured voltage value and nominal voltage value for every voltage level. Rin of voltage meter must be > 10 MΩ.

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1.3 ST7282A5/B5 ADDRESS MAPPING ADDR. Port A Data Direction Reg. Port B Data Direction Reg. Port C Data Direction Reg. Port D Data Direction Reg.

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Port E Data Register Port E Data Direction Register Port E Option Register Port F Data Register Port F Data Direction Register Port F Option Register Port G Data Register Port G Data Direction Register Port G Option Register Port H Data Register Port H Data Direction Register Port H Option Register

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EEPROM read out protected not available (test area) reserved (ST Routram area) user vectors “Not to be used” is mandatory. Any access would modify the functionality.

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2 IMPLEMENTATION REMARKS OF THE DEDICATIONS In this chapter the options of the dedications, which are implemented are described. The dedications are described in detail in the target specs of the dedications. In case of discrepancies between this specification and the specs. of the dedications, this specification is valid. 2.1 Core 2.1.1 Oscillator The oscillator can be used with quartz or ceramic resonator. The pins OSCIN and OSCOUT permit connection to the on chip clock oscillator circuit. OSCIN is the input, OSCOUT the clock oscillator output. A quartz or a ceramic resonator can be...

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Figure 2. External Interrupt Options INTP I1 External Interrupt Options Negative edge and Low level sensitive Negative edge only Positive edge only Positive and negative edge sensitive 2.2 LCD controller/driver The LCD module contains an LCD controller/driver with 20 segment and 16 backplane outputs able to drive up to 20 x 16 = 320 segments. The LCD control logic reads automatically data from the LCD-RAM independently from the ST72 core. Two signals (LCF32K,LCSYNCHINOUT) can be activated on pins PC0, PC1 to connect a slave display chip for expanding the number of segments. To activate...

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2.2.2 External Divider Chain The different display voltage levels are supplied by an external resistor chain as shown in fig. below. Two different configurations with five or four display voltage levels can be chosen. The resistors have to have a good matching within < 1% to avoid DC voltage levels on the liquid crystal device. DC levels trigger electrode reactions on the liquid crystal cell, deteriorating display quality rapidly. Figure 3. External Divider Chain VLCD VLCD

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2.2.2.1 Working with 1/5 Bias Figure 4. Waveform on common and on segment output working with 1/5 Bias VLCD BACKP LANE SELECTED

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2.2.2.2 Working with 1/4 Bias Depending on the selected display material, the operating mode and the display voltage VLCD, it is possible to reduce the LCD resistor chain to 4 resistors, and operate with the 1/4 bias method. If VLCD35 and VLCD25 are connected to the same voltage, the segment and backplane drivers will work in the same way as with 1/5 bias, but the resulting waveforms will look a bit different : Figure 5. Waveform on common and on segment output working with Bias 1/4 VLCD SEGMENT SELECTED SEGMENT SELECTED

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Figure 6. Address Mapping of the LCD-RAM MUX16 Figure 7. Address Mapping of the LCD-RAM MUX8 BP1

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Figure 8. Address Mapping of the LCD-RAM MUX4 2.3 TIMER 4 16 bit autoreload timer with 2 capture inputs connected to PA0, PA1 (see spec. ST7TIM4). The in- put clock of the timer is fosc divided by 2. 2.4 WATCHDOG The WD2 is used to reset the ST7282 B5 after a certain period of time in the range of 2.8 msec up to 184 msec when fOSC = 8.55 MHz is used. WD2 will be activated, if bit0 in Watchdog Reg. (Adr. 12h) is set ("1"). Once WD2 is running, any software access to bit0 in Watchdog Reg. will NOT influence WD2. However, a RESET signal (either externally or caused by WD2) will reset bit0 of...

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SGS-THOMSON ST7282 23Pages

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SGS-THOMSON ST7282
23Pages