S1D13705 Embedded Memory LCD Controller Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice.You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK TECHNICAL MANUAL Issue Date: 01/04/18

Epson Research and Development Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and schematics. • To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representative. Chip Documentation • Technical manual includes Data Sheet, Application Notes, and Programmer’s Reference....

Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK TECHNICAL MANUAL Issue Date: 01/04/18

S1D13705 Embedded Memory LCD Controller The S1D13705 is a color/monochrome LCD graphics controller with an embedded 80K Byte SRAM display buffer. The high integration of the S1D13705 provides a low cost, low power, single chip solution to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices, and Palm-size PCs where board size and battery life are major concerns. Products requiring a “Portrait” display can take advantage of the Hardware Portrait Mode feature of the S1D13705. Virtual and Split Screen are just some of the display modes supported....

GRAPHICS S1D13705 ■ DESCRIPTION Memory Interface • Embedded 80K byte SRAM display buffer. CPU Interface • Direct support for: Hitachi SH-3. Hitachi SH-4. Motorola M68xxx. MPU bus interface with programmable READY. • CPU write buffer. Display Support • 4/8-bit monochrome LCD interface. • Single-panel, single-drive passive displays. • Dual-panel, dual-drive passive displays. • Active matrix TFT / D-TFD interface. • Example resolutions: 640x480 at a color depth of 2 bpp. 640x240 at a color depth of 4 bpp. 320x240 at a color depth of 8 bpp. Clock Source • Single clock input for both pixel and memory...

S1D13705 Embedded Memory LCD Controller Hardware Functional Specification Document Number: X27A-A-001-09 Copyright © 1999, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice.You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected...

Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK Hardware Functional Specification Issue Date: 01/05/22

Epson Research and Development Vancouver Design Center Features . . . . . . . . . . 2.1 Integrated Frame Buffer 2.2 CPU Interface . . . . 2.3 Display Support . . . . 2.4 Display Modes . . . . 2.5 Clock Source . . . . . 2.6 Miscellaneous . . . . 2.7 Package . . . . . . . Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 12 Functional Block Diagram . . . . . 4.1 Functional Block Descriptions . . 4.1.1 Host Interface . . . . . . . . 4.1.2 Memory Controller . . . . . 4.1.3 Sequence Controller . . . . . 4.1.4 Look-Up Table . . . . . . . 4.1.5 LCD Interface . . . ....

Epson Research and Development Vancouver Design Center 7.1.5 Generic #1 Interface Timing . . . . . . . . . . . 7.1.6 Generic #2 Interface Timing . . . . . . . . . . . 7.2 Clock Input Requirements . . . . . . . . . . . 7.3 Display Interface . . . . . . . . . . . . . . . 7.3.1 Power On/Reset Timing . . . . . . . . . . . . . 7.3.2 Power Down/Up Timing . . . . . . . . . . . . 7.3.3 Single Monochrome 4-Bit Panel Timing . . . . 7.3.4 Single Monochrome 8-Bit Panel Timing . . . . 7.3.5 Single Color 4-Bit Panel Timing . . . . . . . . 7.3.6 Single Color 8-Bit Panel Timing (Format 1) . . 7.3.7 Single Color...

Epson Research and Development Vancouver Design Center List of Tables Table 5-1: Summary of Power On/Reset Options . . . . . . . . . . . . . . . . Table 5-2: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . Table 5-3: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . Table 6-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . Table 6-2: Recommended Operating Conditions for Core VDD = 3.3V ± 10% Table 6-3: Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-4: Output Specifications. . . . . . . . . . . . . . . ....

Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK Hardware Functional Specification Issue Date: 01/05/22

Epson Research and Development Vancouver Design Center List of Figures Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 4-1: Figure 5-1: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: Figure 7-10: Figure 7-11: Figure 7-12: Figure 7-13: Figure 7-14: Figure 7-15: Figure 7-16: Figure 7-17: Figure 7-18: Figure 7-19: Figure 7-20: Figure 7-21: Figure 7-22: Figure 7-23: Figure 7-24: Figure 7-25: Figure 8-1: Figure 10-1: Figure 11-1: Figure 11-2: Typical System Diagram (SH-4 Bus). . . . . . . . . . . . . . . ....