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IC Epson S1D13L01 LCD Controller

IC Epson S1D13L01 LCD Controller

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IC Epson S1D13L01 LCD Controller

Product catalog summary

Introduction

Scope: This document is the Hardware Functional Specification for the S1D13L01 Series Simple LCD Controller, aimed at Video Subsystem Designers and Software Developers. It includes timing diagrams, AC and DC characteristics, register descriptions, and power management details.
Operational Overview: The S1D13L01 is a simple LCD controller with a 384K byte display buffer, supporting various CPU interfaces and resolutions, including hardware rotation, Alpha Blending, and Transparency.

Features

Display Resolution: Supports multiple resolutions for single and dual-layer displays.
CPU Interface: Compatible with 8/16-bit direct/indirect and SPI interfaces.
Display Interface: Supports TFT panels with hardware rotation and PIP Layer Flash.

System Implementation

Details on integrating the S1D13L01 into a system, including pin configurations and interface mappings.

Pins

Pinout Diagram: Provides a detailed layout of the pin configurations.
Pin Description: Describes the function of each pin, including host and panel interfaces, clock input, and power connections.

Logic Diagram

Illustrates the logical structure and data flow within the S1D13L01.

Embedded Memory

Memory Map: Details the memory allocation and usage within the controller.
Sample Maximum Resolution: Provides examples of maximum resolution capabilities.

Clocks

Clock Tree: Describes the clock distribution and settings within the system.
PLL Setting: Details the configuration of the Phase-Locked Loop for clock management.

D.C. Characteristics

Absolute Maximum Ratings: Lists the maximum operational limits for the device.
Recommended Operating Conditions: Provides the optimal conditions for device operation.

A.C. Characteristics

Clock Timing: Details the timing requirements for clock signals.
Power Supply Sequence: Describes the power-on and power-off sequences.

Registers

Configuration Registers: Details the settings for configuring the device's operation.
Clock Configuration Registers: Provides settings for clock management.

Indirect and Serial Host Interface Accessing Sequence

Describes the procedures for writing and reading data via indirect and SPI interfaces.

Image Data Formats

RGB Data Formats: Details the supported image data formats for host interfaces.

Look-Up Table Architecture

24 bpp LUT: Describes the architecture for 24-bit per pixel look-up tables.

Display Features

PIP Layer: Supports Picture-in-Picture functionality with transparency and alpha blending.
Rotation: Provides hardware rotation capabilities.

Mechanical Data

Provides physical dimensions and mechanical specifications of the device.

Change Record

Documents any changes or revisions made to the specification.

Overview: The document is a technical specification for the EPSON S1D13L01 Series, a simple LCD controller (LCDC). It details the features, system implementation, pin configurations, and interface options for the device.

Display Features:

The controller supports up to two display layers: Main Layer and PIP (Picture-in-Picture) Layer.
Display resolutions vary based on color depth and layer configuration, with maximum resolutions of 480x272 at 24 bpp for a single layer and 400x240 at 24 bpp for the Main Layer with a PIP Layer at 8 bpp.
Features include independent rotation, alpha blending, transparency, and configurable PIP effects like blink and fade in/out.

CPU and Data Interfaces:

Supports 8/16-bit direct and indirect interfaces, as well as SPI (Mode 0, Mode 3).
Input data formats include RGB 8:8:8, RGB 5:6:5, 8 bpp grayscale, and 8/16/24 bpp with Look-Up Table (LUT).

System Implementation:

Typical system diagrams are provided for various modes, including direct and indirect 16-bit and 8-bit modes, as well as SPI mode.
Each mode has specific pin configurations and connections to generic TFT panels.

Pin Configuration:

The document includes detailed pinout diagrams and descriptions for the QFP15-128pin package.
Pin types are categorized as Input, Output, Bi-Directional, Power, and Ground, with specific functions for each pin in different modes.

Power and Miscellaneous:

Power supply pins include IOVDD for IO power and COREVDD for core power, with additional pins for PLL power and ground.
Miscellaneous pins include test enable and scan enable for production testing, which should be grounded during normal operation.

Configuration Options:

Host interface selection is determined by the CNF[2:0] pins, with options for direct and indirect modes, as well as SPI.
Panel interface mode is specified by register settings, with mappings for 16-bit, 18-bit, and 24-bit generic TFT panels.

Embedded Memory:

The S1D13L01 includes 384K bytes of embedded VRAM for image data storage.

Overview: The document is a technical specification for the EPSON S1D13L01 Series, focusing on its hardware functionalities, including memory mapping, clock settings, and electrical characteristics.

Memory Mapping: The document details the memory allocation for the S1D13L01, specifying that AM, Registers, and LUT are directly mapped. VRAM is 384K Bytes, with different configurations for 1 Layer Mode and 2 Layer Mode. In 1 Layer Mode, all VRAM is assigned to the Main Layer, while in 2 Layer Mode, VRAM is split between Main and PIP Layers. Both modes require 32-bit alignment for start addresses.

Resolution Specifications: Maximum resolutions for different data formats are provided. For example, in 1 Layer Mode, RGB 8:8:8 supports 480x273 resolution, while in 2 Layer Mode, combinations like Main RGB 8:8:8 and PIP 8 bpp + LUT2 support 400x240 resolution.

Clock Settings: The document outlines the clock tree and PLL settings, emphasizing the need for proper configuration to avoid instability. It includes minimum requirements for clock settings and examples of register settings to ensure proper operation.

Electrical Characteristics: Detailed tables provide absolute maximum ratings and recommended operating conditions, including supply voltages and temperature ranges. Electrical characteristics such as input leakage current, output voltages, and trigger voltages are specified for different IOVDD levels.

Timing Requirements: The document includes extensive timing diagrams and tables for various modes, such as Direct and Indirect 16-bit Modes. These sections specify setup and hold times, pulse widths, and other critical timing parameters to ensure proper interfacing and operation.

Power Supply Sequence: Power-on and power-off sequences are described, with timing constraints to ensure proper device initialization and shutdown.

Recommendations: The document advises isolating PLL power supply traces to minimize noise and ensure stable PLL operation. It also highlights the importance of maintaining proper clock jitter and power supply cleanliness.

Overview: The document is a technical specification for the EPSON S1D13L01 Series, focusing on hardware functional specifications for LCD controllers. It includes detailed timing parameters, register configurations, and interface protocols.

1. Timing Specifications:

16-bit and 8-bit Timing: The document provides setup and hold times for various signals such as CS#, WR#, RD#, and DB[15:0] or DB[7:0]. These parameters are crucial for ensuring proper data transfer during read and write cycles.
SPI Timing: Details on SPI timing include chip select setup and hold times, serial clock pulse widths, and data setup and hold times. The SPI data is transmitted MSB first, and the SO line is driven low when no data is present.
TFT Panel Timing: The document outlines timing parameters for driving TFT displays, including horizontal and vertical timing details. Parameters like horizontal display width, non-display periods, and pulse start positions are defined.

2. Register Configuration:

General Registers: Registers start at offset 608XXh, with specific addresses for configuration, clock, panel, and layer settings. The document specifies the power save modes and their impact on register access.
Clock Configuration: The PLL settings are detailed, including lock status, bypass, and enable bits. The document emphasizes the need to be in Power Save Mode 0 before making changes to these registers.
Panel Configuration: Registers for setting horizontal and vertical display parameters are provided, with specific bits allocated for each setting.

3. Function Select Tables:

Indirect 16-bit and 8-bit Mode: Tables specify command and data write/read operations based on control signals like P/C#, WR#, and RD#.
SPI Function Select: Commands for 8-bit and 16-bit read/write operations are defined, with reserved commands noted.

4. Notes and Recommendations:

Ensure the S1D13L01 is in the correct power save mode before accessing certain registers.
Do not access memory or LUT during specific power save modes to avoid conflicts.
For TFT panels, horizontal display width must be set in multiples of 8 pixels.

PLL Configuration and Settings
The document outlines the configuration of the Phase-Locked Loop (PLL) for the S1D13L01 series. The clock to the PLL (PFDCLK) should be between 1MHz and 2MHz. The PFDCLK is calculated using the formula: PFDCLK = CLKI ÷ (M-Divider + 1). The M-Divider settings are detailed in Table 10-3, with ratios ranging from 1:1 to 33:1. The PLL must be disabled before changing the register settings.

PLL Output Configuration
The PLL Output (POCLK) is configured using the L-Counter and N-Counter settings. The formula for POCLK is: POCLK = (L-Counter + 1) x (N-Counter + 1) x PFDCLK. For example, with a CLKI input of 1MHz and a target POCLK of 42MHz, the L-Counter is set to 29h.

Internal Clock Configuration
The Internal Clock Configuration Register (REG[16h]) determines the divide used to generate the Pixel Clock (PCLK) from the Memory Clock (MCLK). The PCLK Divide Selection is detailed in Table 10-5, with ratios from 1:1 to 16:1.

Panel Configuration
The Panel Configuration Registers control various aspects of the LCD panel, including DE Polarity, PCLK Polarity, and Panel Data Width. The Panel Setting Miscellaneous Register (REG[20h]) includes settings for DE Polarity, PCLK Polarity, and Panel Port Enable. The Panel Interface must be enabled before setting the Panel Interface Enable.

Display Settings
The Display Settings Register (REG[22h]) includes settings for TE Output Pin Disable, TE Status, Display Blank, and Software Video Invert. The TE Function can be configured for different modes, such as VNDP and Line Count.

Horizontal and Vertical Display Configuration
The Horizontal Display Width Register (REG[24h]) and Vertical Display Height Register (REG[28h]) specify the display dimensions. The Horizontal Non-Display Period Register (REG[26h]) and Vertical Non-Display Period Register (REG[2Ah]) define the non-display periods.

Sync Signal Configuration
The HS Pulse Width Register (REG[2Ch]) and VS Pulse Width Register (REG[30h]) configure the width and polarity of the horizontal and vertical sync signals. The HS Pulse Start Position Register (REG[2Eh]) and VS Pulse Start Position Register (REG[32h]) specify the start positions of the sync signals.

Layer Configuration
The Layer Configuration Registers manage the synchronous latching of multi-byte layer registers. The Multi-Byte Layer Registers Synchronous Latching Disable bit controls the latching behavior.

Main Layer Configuration

Rotation and Color Depth: The Main Layer can be rotated in increments of 90° (0°, 90°, 180°, 270°) using bits 4-3 of REG[40h]. Color depth options include RGB 8:8:8, RGB 5:6:5, and various LUT configurations, controlled by bits 2-0 of REG[40h].
Start Address: The Main Layer Start Address is specified in REG[42h] and REG[44h], requiring 32-bit alignment.
Dimensions: Width and height are read-only and depend on rotation settings, with values updated after a two-frame delay.

PIP Layer Configuration

Rotation and Color Depth: Similar to the Main Layer, the PIP Layer supports rotation and color depth settings, controlled by REG[50h].
Start Address: Defined in REG[52h] and REG[54h], also requiring 32-bit alignment.
Dimensions and Position: Width, height, and start positions (X, Y) are specified in REG[56h] to REG[5Ch].

PIP Effects and Alpha Blending

Effects: PIP Layer supports various effects like Blink, Fade In/Out, controlled by REG[60h].
Alpha Blending: The blending ratio and steps are managed by REG[62h], allowing dynamic changes during fade effects.

Transparency

Enable/Disable: Controlled by REG[64h], transparency can be toggled on or off.
Key Color: Defined in REG[66h] and REG[68h], used to determine pixel transparency based on color matching.

GPIO Setting Registers
GPIO[3:0] are dedicated pins, while GPIO[15:4] depend on panel type and data width. GPIO pins can be configured as inputs (0b) or outputs (1b). Output configuration allows writing 1b to drive high and 0b to drive low. Input configuration allows reading the pin status. Pull-down resistors can be activated (1b) or deactivated (0b) for each pin.

Look-Up Table Registers
The document details the configuration of Look-Up Tables (LUT1 and LUT2) for color data storage. Each LUT address stores green, blue, and red data components. Access to LUT1 and LUT2 is restricted during PSM0.

Indirect and Serial Host Interface
The indirect interface requires address definition before data operations, supporting burst transfers. Single and burst write/read procedures are illustrated for 16-bit and 8-bit modes. The SPI interface supports Mode 0 and Mode 3, with specific command sequences for read/write operations. The address auto-increments during burst access, and the first byte in read operations is dummy data.

SPI Function Select
Commands for SPI operations include 8-bit and 16-bit read/write, with specific command codes provided. The address for 16-bit operations must be even.

Specifications and Procedures:
The document outlines the hardware functional specifications for the EPSON S1D13L01 Series, focusing on the Simple LCD Controller (LCDC). It includes detailed procedures for SPI 8-bit and 16-bit read sequences to read N words, emphasizing the importance of even-numbered addresses and the use of verbose 5-bit commands.

Image Data Formats:
Chapter 12 discusses various image data formats for the host interface, including RGB 8:8:8, RGB 5:6:5, 24 bpp + LUT, 16 bpp + LUT, and 8 bpp + LUT. Each format is detailed with tables showing data cycles for both 16-bit and 8-bit host interfaces. The document specifies the necessary register settings for each format to ensure proper data handling and display.

Data Expansion and Color Depth:
Data is expanded to 24-bit between VRAM and the panel interface. The document explains how color depth is defined using specific registers, with all image data handled as 24-bits. The master logic outputs 24-bits, and the slave logic removes unused bits.

Look-Up Table Architecture:
Chapter 13 describes the LUT architecture for different color depths, including 24 bpp, 16 bpp, and 8 bpp LUTs. Each layer (Main and PIP) has its own LUT, and the document provides figures illustrating the LUT configurations.

Display Features:
Chapter 14 covers display features such as the PIP (Picture-in-Picture) Layer, transparency, alpha blending, and PIP effects. The PIP Layer can be configured with various effects like Normal, Blink, and Fade, and is displayed on top of the Main Layer. Transparency and alpha blending are also discussed, with specific register settings provided for enabling these features.

Fade and Blink Effects: The document specifies the configuration of blinking and fading effects for PIP (Picture-in-Picture) layers. The blinking period is controlled by specific register bits, and the fade steps are determined by the alpha-blend value increments or decrements. These parameters can be dynamically adjusted to modify the speed of the effects.

Fade Steps: The alpha-blend value can be adjusted in steps of +/-1, +/-2, +/-4, or +/-8, allowing for precise control over the fading effect. The document provides a diagram illustrating the fade-in steps.

PIP Effect State Transitions: The document outlines the transitions between different PIP effect states, such as Blink1, Blink2, Fade In, Fade Out, and Fade In/Out Continuous. It explains how to program the PIP Effect bits to transition between these states and monitor the Blink/Fade Status bit to determine the completion of effects.

Rotation: Both Main and PIP layers can be rotated independently. The location and start addresses for these layers are defined by specific registers, ensuring proper alignment and display.

Operating Modes: The document describes various operating modes for the S1D13L01, including NMM (Normal Mode), PSM0, and PSM1. It provides a summary table of these modes, indicating register accessibility and clock activity.

Mechanical Data: The document includes a section on mechanical data, likely providing dimensions and physical specifications for the hardware.

Contact Information: The document concludes with international contact information for EPSON's sales operations across America, Europe, and Asia.

Catalog excerpts

Hardware Functional Specification Document Number:XA8A-A-001-01 Issue Date: 02/28/14 SEIKO EPSON CORPORATION

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NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted...

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Table of Contents Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Features . . . . 2.1 Display Resolution 2.2 CPU Interface . . 2.3 Input Data Format . 2.4 Display Interface . 2.5 Display Features . 2.6 Miscellaneous . . Chapter 3 Typical System Implementation . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 4 Pins . . . . . . . . . . . . . 4.1 Pinout Diagram . ....

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Chapter 11 Indirect and Serial Host Interface Accessing Sequence . . . . 11.1 Indirect Interface . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 Write Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.2 Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.1 Write Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 Read Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 12 Image Data Formats . . . . . . 12.1 Image Data Formats...

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12.2 Data Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12.3 Color Depth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Chapter 13 Look-Up Table Architecture 13.1 24 bpp LUT . . . . . . . . . . 13.2 16 bpp LUT . . . . . . . . . . 13.3 8 bpp LUT in Color Mode . . . . Chapter 14 Display Features . . . . . . 14.1 PIP (Picture-in-Picture) Layer . . 14.2 Transparency . . . . . . . . . 14.3 Alpha Blending . . . . . . . . 14.4 PIP Effects . . . . . . . . . . 14.4.1 Blinking and Fading Effects . 14.4.2 Blink/Fade Period . . . . . . 14.4.3 Fade Steps . ....

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S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Chapter 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13L01 Series Simple LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check for the latest revision of this document before beginning any development. The latest revision can be downloaded at vdc.epson.com. We appreciate your comments on our documentation. Please contact...

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Chapter 2 Features 2.1 Display Resolution • 384K bytes of embedded VRAM for storing the image data • Display Resolutions for one layer display (Main Layer Only): • Up to 480x272 at 24 bpp • Up to 800x480 at 8 bpp • Display Resolutions for two layer display (Main and PIP Layer): • Up to 400x240 at 24 bpp (Main Layer) and 400x240 at 8 bpp (PIP Layer) 2.2 CPU Interface • 8/16-bit Direct interface • 8/16-bit Indirect interface • SPI (Mode 0, Mode 3) 2.3 Input Data Format • RGB 8:8:8, RGB 5:6:5, 8 bpp grayscale, or 8/16/24 bpp with Look-Up Table (LUT) 2.4 Display Interface • Active Matrix TFT panels...

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2.5 Display Features • Up to two display layers: • Main Layer • 8/16/24 bpp color depths with optional Look-up Table (LUT) • Independent rotation (0, 90, 180, 270° counter-clockwise) • PIP Layer • 8/16/24 bpp color depths with optional Look-up Table (LUT) • Independent rotation (0, 90, 180, 270° counter-clockwise) • Configurable PIP Effects allow automatic blink and fade in/out effects • Alpha Blending • Transparency • Look-up Tables for Main and PIP Layers (256 address x 24 bpp) 2.6 Miscellaneous • Single Clock Input: CLKI • Embedded PLL • Software initiated Power Save Modes • General Purpose...

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Chapter 3 Typical System Implementation Direct 16-bit Mode 1 Figure 3-1: Typical System Diagram (Direct 16-bit Mode 1, Panel Generic TFT 16-bit) Figure 3-2: Typical System Diagram (Direct 16-bit Mode 2, Generic TFT 18-bit) S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Figure 3-3: Typical System Diagram (Indirect 16-bit Mode 1, Generic TFT 16-bit) Figure 3-4: Typical System Diagram (Indirect 16-bit Mode 2, Generic TFT 18-bit) S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Figure 3-5: Typical System Diagram (Direct 8-bit, Generic TFT 16-bit) Figure 3-6: Typical System Diagram (Indirect 8-bit, Generic TFT 18-bit) S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Figure 3-7: Typical System Diagram (SPI, Generic TFT 24-bit) S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Chapter 4 Pins 4.1 Pinout Diagram IOVDD NC CLKI GND NC DB15 DB14 DB13 DB12 DB11 DB10 NC DB9 DB8 COREVDD GND NC DB7 DB6 DB5 DB4 NC DB3 DB2 NC DB1 IOVDD DB0 CS# WR# NC RD# PDT9 PDT8 PDT7 PDT6 GND NC PDT5 PDT4 PDT3 PDT2 NC PDT1 PDT0 IOVDD PCLK NC COREVDD GND DE HS VS PLLVDD VCP PLLGND NC NC Figure 4-1 S1D13L01 Pinout Diagram (QFP15-128pin) - Top View S1D13L01 Series Hardware Functional Specification (Rev. 1.0)

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Input Output Bi-Directional (Input/Output) Power pin Analog Power pin Ground Analog Ground RESET# / Power Save State H = High level output L = Low level output Hi-Z = High Impedance Q = Output Pin, retains output state QB = IO Pin, if configured as output retains state Table 4-1: Cell Description Item H System LVCMOS Schmitt Input Buffer with Fail Safe H System LVCMOS Schmitt Input Buffer with pull-down resistor and Fail Safe H System LVCMOS Schmitt Input Buffer with pull-up resistor and Fail Safe H System LVCMOS Input Buffer with pull-down resistor and Fail Safe H System LVCOMOS Output buffer...

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IC Epson S1D13L01 LCD Controller

IC Epson S1D13L01 LCD Controller

Catalog excerpts

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