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IC EPSON S1D13700 LCD Controller

IC EPSON S1D13700 LCD Controller

Product catalog summary

Introduction
This document provides the hardware functional specifications for the S1D13700F01 Embedded Memory Graphics LCD Controller, detailing its capabilities and intended applications.

Features
The controller includes internal memory, a host CPU interface, support for various display modes, character generation capabilities, power management features, and a clock source. It is designed for integration into larger systems.

System Diagrams
System diagrams illustrate the architecture and functional blocks of the controller, showing component interactions.

Pins
The document details the pinout diagram and descriptions, including host interface, LCD interface, clock input, and power and ground connections.

D.C. and A.C. Characteristics
Specifications for direct current (D.C.) and alternating current (A.C.) characteristics are provided, including clock timing, reset timing, and CPU interface timing.

Memory Mapping
The memory mapping section describes how memory is organized and accessed within the controller.

Clocks
Details on the clock system, including diagrams and descriptions of system and FPSHIFT clocks, as well as the oscillator circuit.

Registers
The register set is outlined, including system control, display control, drawing control, and grayscale registers.

Indirect Addressing
This section explains the system control functions accessible through indirect addressing, including system settings, power save, display on/off, and scrolling.

Display Control Functions
Character and screen configuration, cursor control, memory-to-display relationships, and scrolling functions are detailed.

Character Generator
Characteristics of the internal character generator and RAM, along with addressing examples and character codes, are discussed.

Microprocessor Interface
The system bus interface is described for generic, M6800, and MC68K family microprocessors.

Application Notes
Includes register initialization parameters, display mode setting examples, system overview, smooth horizontal scrolling, and layered display attributes.

Specifications
The document outlines the hardware functional specifications for the S1D13700F01, focusing on character and graphics display capabilities.

Procedures
1. CGRAM Addressing: Provides an example of defining a pattern for a character using CGRAM.
2. Microprocessor Interface: Describes the system bus interface and signal states for interfacing with different microprocessor families.
3. Initialization: Offers a detailed initialization procedure for setting up the display.

Standards and Norms
The document specifies the use of CGRAM for character codes and the conditions under which different bits per pixel (bpp) are supported.

Recommendations
1. Ensure correct TC/R settings to avoid display issues.
2. Use the appropriate crystal frequency for fSYSCLK calculations.

Key Data from Tables and Figures
- Figure 13-1: Illustrates row select address configurations.
- Table 14-1 to 14-3: Provide signal states for interfacing with different microprocessor families.

Critical Information
- The document emphasizes the importance of correct initialization and configuration settings to ensure proper display functionality.

Specifications and Procedures
The document outlines the hardware functional specifications for the S1D13700F01, a medium-resolution LCD controller.

Display Mode Settings
The S1D13700F01 supports a 320 x 200 pixel display with a single-panel drive.

Smooth Horizontal Scrolling
The controller supports smooth horizontal scrolling by adjusting the horizontal pixel scroll parameter.

Layered Display Attributes
The S1D13700F01 enhances monochrome LCD displays with features like inverse display, half-tone display, and flashing attributes.

Graphic Display and Character Generation
The document details procedures for displaying 16 x 16 pixel characters and Kanji characters using the internal character generator.

Power Save Mode
The S1D13700F01 includes a power save mode that reduces power consumption by disabling certain functions while maintaining register values.

Mechanical Data
Mechanical specifications for the S1D13700F01 are provided, including dimensions and pin configurations.

References and Support
The document lists additional resources and contact information for technical support and sales across various regions.

Change Record
Revisions and changes from previous versions are highlighted, including updates to pin table definitions and interface timing diagrams.

Overview
This document outlines the revisions and updates made to the S1D13700F01 Hardware Functional Specification.

Key Revisions

Timing Adjustments: Several timing parameters have been adjusted.
Interface and Timing Diagrams: Updates include removing references to MR# and adjusting diagrams.
Register Modifications: Changes to register values include increasing the maximum Character Bytes Per Row.
System Set Command: Clarifications and additional notes have been added regarding the SYSTEM SET command.
New Sections and Notes: Introduces use cases for Horizontal Pixel Scrolling.
Mechanical and Sales Information: Updates to mechanical drawing sizes and sales information.
Typographical Corrections: Various sections have been corrected for typos.

Additional Notes
The document also includes updates to the reset timing section, clarifications on oscillator usage, and adjustments to the Host Interface Pin Mapping Table.

Catalog excerpts

S1D13700F01 Embedded Memory Graphics LCD Controller Hardware Functional Specification Document Number: X42A-A-002-04 Status: Revision 4.05 Issue Date: 2005/12/13 © SEIKO EPSON CORPORATION 2004 - 2005. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners

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Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2005/12/13 Revision 4.05

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Epson Research and Development Vancouver Design Center Features . . . . . . . . . 2.1 Internal Memory . . 2.2 Host CPU Interface . 2.3 Display Support . . . 2.4 Display Modes . . . 2.5 Character Generation 2.6 Power . . . . . . 2.7 Clock Source . . . . 2.8 Package . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pins . . . . . . . . . . . . . . . . . 5.1 Pinout Diagram . . . . . . . . 5.2 Pin Descriptions . . . . . . . 5.2.1 Host Interface . . . . . . . . 5.2.2 LCD Interface . . . . . . . . 5.2.3 Clock Input . . . . . . . . . 5.2.4 Power And...

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Epson Research and Development Vancouver Design Center Clocks . . . . . . . . . . . 9.1 Clock Diagram . . . . 9.2 Clock Descriptions . . 9.2.1 System Clock . . 9.2.2 FPSHIFT Clock . 9.3 Oscillator Circuit . . . 10 Registers . . . . . . . . . . . . . . . . 10.1 Register Set . . . . . . . . . . . 10.2 Register Restrictions . . . . . . . 10.3 Register Descriptions . . . . . . . 10.3.1 System Control Registers . . . . 10.3.2 Display Control Registers . . . . 10.3.3 Drawing Control Registers . . . 10.3.4 Gray Scale Register . . . . . . . 11 Indirect Addressing . . . 11.1 System Control . . . 11.1.1...

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Epson Research and Development Vancouver Design Center 12.3.2 Cursor Movement . . . . . . . . . . . . . . 12.3.3 Cursor Display Layers . . . . . . . . . . . . 12.4 Memory to Display Relationship . . . . . . . 12.5 Scrolling . . . . . . . . . . . . . . . . 12.5.1 On-Page Scrolling . . . . . . . . . . . . . . 12.5.2 Inter-Page Scrolling . . . . . . . . . . . . . 12.5.3 Horizontal Wraparound Scrolling . . . . . . 12.5.4 Bi-directional Scrolling . . . . . . . . . . . 12.5.5 Scroll Units . . . . . . . . . . . . . . . . . 12.5.6 Horizontal Pixel Scrolling (HDOTSCR) . . 13 Character Generator . . ....

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17 Power Save Mode Epson Research and Development Vancouver Design Center 18 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 20 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 20.1 Epson LCD Controllers (S1D13700F01) . . . . . . . . . . . . . . . . . . . 129 20.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Hardware Functional Specification Issue Date: 2005/12/13 Revision 4.05

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Epson Research and Development Vancouver Design Center 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13700F01. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on...

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Epson Research and Development Vancouver Design Center 2 Features 2.1 Internal Memory • Embedded 32K bytes of SRAM display memory 2.2 Host CPU Interface • Direct Address Bus support for: • Generic Bus (Z80 family) microprocessor interface • MC68K family microprocessor interface • Indirect Address Bus support for: • Generic Bus (Z80 family) microprocessor interface • MC68K family microprocessor interface • M6800 family microprocessor interface • 8-bit CPU data bus interface 2.3 Display Support • 4-bit monochrome LCD interface • Maximum resolutions supported: 640x240 at 1 bpp 320x240 at 2 bpp 240x160...

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Epson Research and Development Vancouver Design Center 2.5 Character Generation • 160, 5x7 pixel characters in embedded mask-programmed character generator ROM (CGROM) • Up to 64, 8x8 pixel characters in character generator RAM (CGRAM) • Up to 256, 8x16 pixel characters in embedded character generator RAM (when CGROM is not used) 2.6 Power • Software initiated power save mode • Low power consumption • CORE VDD 3.0 to 3.6 volts • IO VDD 3.0 to 5.5 volts 2.7 Clock Source • Two terminal crystal or Single Oscillator input Input Clock (maximum 60 MHz) FPSHIFT Clock (maximum 15 MHz) 2.8 Package • TQFP13...

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Epson Research and Development Vancouver Design Center WAIT# RESET# Figure 3-1 Indirect Generic to S1D13700F01 Interface Example WAIT# RESET# Figure 3-2 Direct Generic to S1D13700F01 Interface Example Hardware Functional Specification Issue Date: 2005/12/13 Revision 4.05

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Epson Research and Development Vancouver Design Center Figure 3-3 Indirect MC68K to S1D13700F01 Interface Example Figure 3-4 Direct MC68K to S1D13700F01 Interface Example Hardware Functional Specification Issue Date: 2005/12/13

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Epson Research and Development Vancouver Design Center Figure 3-5 Indirect M6800 to S1D13700F01 Interface Example Hardware Functional Specification Issue Date: 2005/12/13 Revision 4.05

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Epson Research and Development Vancouver Design Center 4 Functional Block Diagram FPDAT[3:0] FPSHIFT XECL YSCL FPLINE FPFRAME MOD YDIS Display Address Generator Cursor Address Controller Layered Controller DotClock Generator Internal Clock Microprocessor Interface Host Microprocessor Figure 4-1 Functional Block Diagram Hardware Functional Specification Issue Date: 2005/12/13

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IC EPSON S1D13700 LCD Controller

IC EPSON S1D13700 LCD Controller

Catalog excerpts

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