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EPSON SED1335 LCD Controller

EPSON SED1335 LCD Controller
95Pages

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No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is...

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SED1335 Series Technical Manual

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SED1335 Series Technical Manual

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SED1335 Series Technical Manual

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The SED1335 series is a controller IC that can display text and graphics on LCD panel. The SED1335 series can display layered text and graphics, scroll the display in any direction and partition the display into multiple screens. The SED1335 series stores text, character codes and bitmapped graphics data in external frame buffer memory. Display controller functions include transferring data from the controlling microprocessor to the buffer memory, reading memory data, converting data to display pixels and generating timing signals for the buffer memory, LCD panel. The SED1335 series has an...

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BLOCK DIAGRAM Input/Output Register Display Address Controller Refresh Counter Layered Controller Microprocessor Interface Cursor Address Controller SED1335 Series Technical Manual

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VD4 VD5 VD6 VD7 YSCL YD YDIS WF LP VSS XSCL XECL XD0 XD1 XD2 SED1335 Series Technical Manual

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Output Output Output Input — VRAM write signal Memory control signal VRAM read signal Reset No connection 8080 family: Read signal 6800 family: Enable clock (E) 8080 family: Write signal 6800 family: R/W signal 8080 or 6800 family interface select 8080 or 6800 family interface select Oscillator connection Oscillator connection Chip select Data type select 2.7 to 5.5V supply Input Output Input Input Supply Output Output Output Supply Output Output Output Output Input/output D0 to D7 XD0 to XD3 XECL XSCL VSS LP WF YDIS YD YSCL VD0 to VD7 Data bus X-driver data X-driver enable chain clock...

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5.2. Pin Functions 5.2.1. Power supply Pin Name VDD VSS Function 2.7 to 5.5V supply. This may be the same supply as the controlling microprocessor. Ground Note: The peak supply current drawn by the SED1335 series may be up to ten times the average supply current. The power supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47 µF decoupling capacitors that have good high-frequency response near the device’s supply pins. Function Crystal connection for internal oscillator (See section 13). This pin can be driven by an external...

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Function 8080 family interface A0 Status flag read Display data and cursor address read Display data and parameter write Command write Status flag read Display data and cursor address read Display data and parameter write Command write When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The SED1335 series output buffers are enabled when this signal is active. When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock. Data is read from or written to the SED1335 series when this clock goes HIGH. When the 8080 family...

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5.2.5. LCD drive signals In order to provide effective low-power drive for LCD matrixes, the SED1335 series can directly control both the X- and Y-drivers using an enable chain. Pin Name 4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver chips. XSCL=clock XECL LP=latch The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the X-drivers. To conserve power, this clock halts between LP and the start of the following display line (See section 6.3.7). The falling edge of XECL triggers the enable chain cascade for...

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Supply voltage Register data retention voltage Input leakage current Output leakage current Operating supply current Quiescent supply current Oscillator frequency External clock frequency Oscillator feedback resistance TTL HIGH-level input voltage LOW-level input voltage Measured at crystal, 47.5% duty cycle. See note 6. HIGH-level output voltage LOW-level output voltage CMOS HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VIHC VILC VOHC LOW-level output voltage Open-drain LOW-level output voltage Schmitt-trigger Rising-edge threshold voltage Falling-edge...

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VDD = 2.7 to 4.5 V, VSS = 0 V, Ta = –20 to 75˚C unless otherwise noted Rating Parameter Supply voltage Register data retention voltage Input leakage current Output leakage current Operating supply current Quiescent supply current Oscillator frequency External clock frequency Oscillator feedback resistance HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Open-drain LOW-level output voltage Schmitt-trigger Rising-edge threshold voltage...

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6.3. SED1335F Timing Diagrams 6.3.1. 8080 family interface timing AO, CS tAW8 Parameter Address hold time Address setup time System cycle time Strobe pulsewidth Data setup time Data hold time RD access time Output disable time Note: For memory control and system control commands: tCYC8 = 2tC + tCC + tCEA + 75 > tACV + 245 For all other commands: tCYC8 = 4tC + tCC + 30

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6.3.2. 6800 family interface timing E tCYC6 tAW6 Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH. System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable pulsewidth Note: For memory control and system control commands: tCYC6 = 2tC + tEW + tCEA + 75 > tACV + 245 For all other commands: tCYC6 = 4tC + tEW + 30

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6.3.3. Display memory read timing EXTΦ0 tC tW tAHC tRCH tASC tAHC tRCS Parameter Clock period VCE HIGH-level pulsewidth VCE LOW-level pulsewidth Read cycle time 3tC — 3t C — Address setup time to — tC – 100 — tC – 70 falling edge of VCE Address hold time from — 2tC – 40 — 2tC – 30 falling edge of VCE Read cycle setup time to tC – 45 — tC – 60 — falling edge of VCE Read cycle hold time — 0.5tC — 0.5tC from rising edge of VCE Address access time — 3tC – 100 — 3tC – 115 VCE access time — 2tC – 80 — 2tC – 90 Output data hold time 0 — 0 — VCE to data off time 0 — 0 —

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EPSON SED1335 LCD Controller 95Pages

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EPSON SED1335 LCD Controller
95Pages