S1D13709 Embedded Memory Graphics LCD Controller Hardware Functional Specification Document Number: XA8A-A-001-01 Status: Revision 1.0 Issue Date: 2014/1/20
Open the catalog to page 1SEIKO EPSON Microdevices Operation Division NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license...
Open the catalog to page 2SEIKO EPSON Microdevices Operation Division Hardware Functional Specification Issue Date: 2014/1/20
Open the catalog to page 3SEIKO EPSON Microdevices Operation Division Features . . . . . . . . . 2.1 Internal Memory . . 2.2 Host CPU Interface . 2.3 Display Support . . 2.4 Display Modes . . . 2.5 Character Generation 2.6 Power . . . . . . 2.7 Clock Source . . . 2.8 Package . . . . . System Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.1 Host Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 LCD Interface Connections . . . . . . . . . . . . . . . . . . . . . . . . . .14 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . ....
Open the catalog to page 4SEIKO EPSON Microdevices Operation Division 7.4.1 Generic Bus Indirect Interface with WAIT# Timing . . . . . . . . 7.4.2 Generic Bus Direct Interface with WAIT# Timing . . . . . . . . . 7.4.3 Generic Bus Indirect Interface without WAIT# Timing . . . . . . 7.4.4 Generic Bus Direct Interface without WAIT# Timing . . . . . . . 7.4.5 MC68K Family Bus Indirect Interface with DTACK# Timing . . . 7.4.6 MC68K Family Bus Direct Interface with DTACK# Timing . . . 7.4.7 MC68K Family Bus Indirect Interface without DTACK# Timing . 7.4.8 MC68K Family Bus Direct Interface without DTACK# Timing . . 7.4.9 M6800...
Open the catalog to page 5SEIKO EPSON Microdevices Operation Division 11.1.6 CSRDIR . . . . . . 11.1.7 OVLAY . . . . . . 11.1.8 CGRAM ADR . . . 11.1.9 HDOT SCR . . . . 11.1.10 CSRW . . . . . . . 11.1.11 CSRR . . . . . . . 11.1.12 GRAYSCALE . . . 11.1.13 ID . . . . . . . . . 11.1.14 PLL SET . . . . . . 11.1.15 TFT-IF SET 1 . . . 11.1.16 TFT-IF SET 2 . . . 11.1.17 HDOT SCR SYNC 11.1.18 PALETTE . . . . . 11.1.19 OUTDRIVE . . . . 11.1.20 Memory Control . . 12 Display Control Functions . . . . . . . . . . . . . . . 12.1 Character Configuration . . . . . . . . . . . . . 12.2 Screen Configuration . . . . . . . . . . . . . ....
Open the catalog to page 6SEIKO EPSON Microdevices Operation Division 13.2.1 CGRAM Addressing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 13.3 Character Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 14 Microprocessor Interface . . . . . 14.1 System Bus Interface . . . . . 14.1.1 Generic . . . . . . . . . . . 14.1.2 M6800 Family . . . . . . . . 14.1.3 MC68K Family . . . . . . . 15 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.1 Register Initialization/Initialization Parameters . . . . . . . . . . . . . . . . . 148 15.1.1 SYSTEM...
Open the catalog to page 7SEIKO EPSON Microdevices Operation Division 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13709. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This document is updated as appropriate. Please check the Epson Research and Development Website at vdc.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation....
Open the catalog to page 8SEIKO EPSON Microdevices Operation Division 2 Features 2.1 Internal Memory • Embedded 32K bytes of SRAM display memory 2.2 Host CPU Interface • Direct Address Bus support for: • Generic Bus (Z80 family) microprocessor interface • MC68K family microprocessor interface • Indirect Address Bus support for: • Generic Bus (Z80 family) microprocessor interface • MC68K family microprocessor interface • M6800 family microprocessor interface • 8-bit CPU data bus interface 2.3 Display Support • STN-LCD • 4-bit monochrome LCD interface • Maximum resolutions supported: 640x240 at 1 bpp 320x240 at 2 bpp 240x160...
Open the catalog to page 9SEIKO EPSON Microdevices Operation Division 2.4 Display Modes • 1/2/4 bit-per-pixel color depth support • Text, graphics and combined text/graphics display modes • Three overlapping screens in graphics mode • Programmable cursor control • Smooth horizontal scrolling of all or part of the display in monochrome mode • Smooth vertical scrolling of all or part of the display in all modes • Color Palette mode for the TFT interface 2.5 Character Generation • 160, 5x7 pixel characters in embedded mask-programmed character generator ROM (CGROM) • Up to 64, 8x8 pixel characters in character generator...
Open the catalog to page 10SEIKO EPSON Microdevices Operation Division 3 System Diagrams 3.1 Host Interface Connections S1D13709 Figure 3-1 Indirect Generic to S1D13709 Interface Example WAIT# RESET# Figure 3-2 Direct Generic to S1D13709 Interface Example Hardware Functional Specification Issue Date: 2014/1/20
Open the catalog to page 11SEIKO EPSON Microdevices Operation Division Figure 3-3 Indirect MC68K to S1D13709 Interface Example Figure 3-4 Direct MC68K to S1D13709 Interface Example Hardware Functional Specification Issue Date: 2014/1/20 Revision 1.0
Open the catalog to page 12SEIKO EPSON Microdevices Operation Division Figure 3-5 Indirect M6800 to S1D13709 Interface Example Hardware Functional Specification Issue Date: 2014/1/20
Open the catalog to page 13SEIKO EPSON Microdevices Operation Division FPSHIFT FPFRAME FPLINE FPDRDY Figure 3-6 S1D13709 to TFT-LCD Example (Gray Scale Mode, REG[34h]bit1 = 0) FPSHIFT FPFRAME FPLINE FPDRDY Figure 3-7 S1D13709 to TFT-LCD Example (Color Palette Mode, REG[34h]bit1 = 1) Hardware Functional Specification Issue Date: 2014/1/20 Revision 1.0
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