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Avant SBN6400G LCD Driver

Avant SBN6400G LCD Driver
34Pages

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DATA SHEET To improve design and/or performance, Avant Electronics may make changes to its products. Please contact Avant Electronics for the latest versions of its products

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Avant Electronics The SBN6400G is a 64-COMMON driver, designed to be paired with the SBN0064G 64-SEGMENT driver to drive a dot-matrix STN LCD panel. Functionally, the SBN6400G includes 64 COMMON drivers, on-chip RC oscillator, a 64-bit bi-directional shift register, and timing generation circuit. The RC oscillator needs only an external resistor and capacitor. The timing generation circuit generates clocks and display control signals for both the SBN6400G and the SBN0064G. To expand COMMON number, the SBN6400G can be cascaded in master-slave connection. 1.2 • To be paired with the SBN0064G...

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Avant Electronics Ordering information Ordering information PRODUCT TYPE

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Avant Electronics 64-COMMON Driver for Dot-Matrix STN LCD FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION Functional block diagram 64-bits output Driver 64-bits Level Shifter High Voltage Circuit 64-bit, bi-directional shift register COMMON Shift Direction, Phase Selection Timing Generation Circuit Fig.1 Functional Block Diagram

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Avant Electronics PIN(PAD) ASSIGNMENT, PAD COORDINATES, SIGNAL DESCRIPTION The SBN6400G pinning diagram (LQFP100 or QFP100)

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Avant Electronics Chip size : 3999 μm x 3799 μm. Pad size: 90 μm x 90 μm. The total of pad number is 92. The chip ID is located at the right middle part of the chip. The chip ID is 12001. The die origin is at the center of the chip. (5) For chip_on_board bonding, chip carrier should be connected to VDD or left open. Chip carrier is the metal pad to which the die is attached.

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Avant Electronics

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Avant Electronics Signal description Table 3 Pin signal description To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V . Pin number DESCRIPTION COMMON outputs. The output voltage level of COMMON outputs are decided by the combination of the alternating frame signal (M) and the internal Shift Register Output. Depending on the value of M and the Shift Register Output, a single voltage level is selected from V0, V1, V4, or V5 for COMMON driver, as shown in Fig. 4. M Internal Shift Register Fig.4 COMMON output voltage level External negative power...

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Avant Electronics 64-COMMON Driver for Dot-Matrix STN LCD Pin number DESCRIPTION Display duty selection inputs. These two inputs are used to select display duty cycle when the SBN6400G operates in master mode. These pins are not valid in slave mode and should be connected to VDD. Pins of the on-chip RC oscillator for connection to external resistor and capacitor. When operating in slave mode, the device’s C and R terminals should be left open and its CR terminal should be connected to VDD. Instead of the RC oscillator, if an external clock source is to be used, then this clock source should...

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Avant Electronics 64-COMMON Driver for Dot-Matrix STN LCD Pin number DESCRIPTION Shift clock for the internal 64-bit, bi-directional shift register. The time duration of each COMMON output is equal to one clock period of the CL clock. External LCD Bias voltage. These terminals should be connected to V1, V4, V5, and VDD, respectively, of the external LCD bias circuit, and the condition VDD≥V1≥V2≥V3≥V4≥V5 must always be met. These terminals are internally connected to V1L, V4L, V5L, and V0L, respectively. For package type, these pins should be left open. For die, there is no NC pad. data sheet

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Avant Electronics FUNCTIONAL DESCRIPTION When operating in master mode, the SBN6400G’s on-chip RC-type oscillator is used to provide clocks and necessary control signals to itself, its slave, and the SBN0064G SEGMENT Driver. External resistor Rf and capacitor Cf need to be connected across R, CR, and C, as shown in Fig. 5. The recommended value for Rf is 33K ohm and that for Cf is 20 pF. During PCB layout, the resistor and the capacitor should be placed as close to the SBN6400G as possible, such that stray capacitance, inductance, and resistance can be minimized. Note: (1) When operating in...

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Avant Electronics RC-oscillator Frequency Selection (FS) When the RC oscillator frequency is 550 KHz, FS should be connected to VDD. When the RC oscillator frequency is below 300 KHz, FS should be connected to VSS. In the both cases, the purpose of this input is to make frame frequency approximately equal to 70 Hz. Usually, 550 KHz operation is recommended. 4.3 Timing Generation The SBN6400G’s internal timing generation circuit is shown in Fig. 6. When M/S=1, the SBN6400G operates in Master Mode, sends M and CL to its slave, and sends M, CL, FRM, CLK1, and CLK2 to the SBN0064G. When M/S=0,...

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Avant Electronics Phase relation between CL and COMMON outputs The PSEL input is used to select the phase relation between CL clock and COMMON outputs. The CL clock is the shift clock to the internal 64-bit, bi-directional Shift Register. A CL clock period is the time duration for displaying a horizontal line of LCD pixels. If PSEL=H, the COM0 starts from the rising edge of CL clock. If PSEL=L, then COM0 starts from the falling edge of CL, as shown in Fig. 7. Usually, it is recommended that PSEL be connected to VDD. Fig.7 Phase relation between COMMON and CL, as decided by PSEL

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Avant Electronics Master/Slave connection The SBN6400G can be cascaded in master-slave connection to expand the total number of COMMONs. When a device is selected as master, its DIO1, DIO2, M, and CL are all in output state. Its M output and CL output should be connected to its slave and its M, CL, FRM, CLK1 and CLK2 should be connected to the SBN0064G. To next stage or open Fig.8 Master/Slave connection with SHL=1 4.7 COMMON output sequence The COMMON output sequence is decided by both the M/S and the SHL inputs, as shown in Table 6. Table 6 COMMON output sequence in master-slave...

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Avant Electronics LCD BIAS AND COMMON OUTPUT VOLTAGE A typical LCD bias circuit for 1/64 display duty is shown in Fig. 9. The condition VDD≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 must always be met. The maximum allowed voltage for LCD bias (VDD-V5) is 13 volts. Note that V0 should be connected to VDD. RECOMMENDED VALUE (1) V0 should always be connected to VDD. (2) For cascading application, it is recommended that a buffer be added for each of V1, V2, V3, V4, and V5. For 64 COM x 64 SEG application, these buffers are not needed. (3) The LCD bias voltage (VLCD = V0 - V5) should not exceed 13 volts, without...

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Avant SBN6400G LCD Driver 34Pages

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Avant SBN6400G LCD Driver
34Pages