DATA SHEET SBN0064G Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory To improve design and/or performance, Avant Electronics may make changes to its products. Please contact Avant Electronics for the latest versions of its products

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory 1 The SBN0064G is a 64-SEGMENT driver with 64-row x64 column (4096-bit) on-chip Display Data Memory. It is designed to be paired with the SBN6400G 64-COMMON driver to drive a STN LCD panel. The on-chip Display Data Memory is for storing display data. Dot-matrix mapping method is used. A “0” stored in the Display Data Memory bit corresponds to an OFF-pixel on the LCD panel; a “1” stored in the Display Data Memory bit corresponds to an ON-pixel on the LCD panel. Display on the LCD panel is controlled...

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory 1.3 Ordering information Ordering information PRODUCT TYPE

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory FUNCTIONAL BLOCK DIAGRAM AND DESCRIPTION Functional block diagram High Voltage Circuit Mapping Circuit CSM Display Data RAM output latch Display ON/OFF Register Display Start Line Register 64 row x 64column (4096 bits) Display Data Memory Line Address Decoder Page Address Register Column Address Register Status Register Column Address Decoder Display Data RAM Access Control Display Data Read/Write Control Display Control Clock and display control Microcontroller Interface Command Decoder Fig.1 Functional...

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory 3 PIN(PAD) ASSIGNMENT, PAD COORDINATES, SIGNAL DESCRIPTION The SBN0064G pinning diagram (LQFP100)

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory The total pad number is 97. The chip ID is located at the lower left part of the chip. The chip ID of is 18005. The die origin is at the center of the chip. (5) For chip_on_board bonding, chip carrier should be connected to VDD or left open. Chip carrier is the metal pad to which the die is attached.

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory 3.3

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory 3.4 Signal description Table 3 Pad signal description To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V . Pad number DESCRIPTION Column/Segment Mapping. This signal controls the mapping relation between the column output of the Display Data Memory and the SBN0064G’s segment output. If CMS=1, the mapping is called Normal Mapping. The mapping relation is that Columns 0, 1, 2,...,62,63 of the Display Data Memory are mapped to Segments 0, 1, 2,..., 62,...

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory Pad number DESCRIPTION External LCD Bias voltage. Note that V0L, V2L, V3L, and V5L must be connected to external bias voltages VDD, V2, V3, and V5, respectively, and the condition VDD≥V1≥V2≥V3≥V4≥V5 must always be met. In addition, VLCD (VDD - V5) should not exceed 13 volts. Ground. Bi-direction, tri-state 8-bit parallel data bus for interface with a host microcontroller. This data bus is for data transfer between the host microcontroller and the SBN0064G. Chip Selection To enable selecting the...

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory 4 A SBN6400G and SBN0064G-based display system is shown in Fig. 5. The SBN6400G contains timing generation circuit and 64 COMMON drivers. The timing generation circuit generates operating clocks and display control signals (frame signal FRM , COMMON scan signal CL, and AC frame signal M), for itself and the SBN0064G. The SBN0064G contains 64 SEGMENT drivers, Display Data Memory, and interface circuit with a host microcontroller. Data bus Microcontroller Interface Display Data Memory Host microcontroller...

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory 5 INTERFACE WITH A HOST MICROCONTROLLER Interface signals and operation The interface signals between the host microcontroller and the SBN0064G are data bus and control bus. The data bus is an 8-bit (DB0~DB7) bi-directional bus. The control bus is composed of the following signals: C/D, E, and R/W. By means of data bus and control bus, the host microcontroller can write data to or read data from the Display Data Memory, can program the internal registers, and can read status of the SBN0064G. It...

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory Table 4 lists the setting for control bus and the types of data transfer. Table 4 Interface signals and types of data transfer Types of data transfer The host microcontroller reads data from the Display Data Memory. The host microcontroller writes data to the Display Data Memory The host microcontroller reads the Status Register. The host microcontroller programs an internal register. Interface Timing (Writing to or reading from the SBN0064G) Please refer to Fig. 16 and Fig. 17 for interface timing...

Avant Electronics Dot-matrix STN LCD 64-SEGMENT Driver with 64-row x 64-column Display Data Memory 6 DISPLAY DATA MEMORY AND LCD DISPLAY The Display Data Memory is a static memory bit(cell) array of 64-row x 64-column. So, the total bit number is 64 x 64 = 4096 bits (512 bytes). Each bit of the memory is mapped to a single pixel (dot) on the LCD panel. A “1” stored in the Display Data Memory bit corresponds to an ON pixel (black dot in normal display). A “0” stored in the Display Data Memory bit corresponds to an OFF pixel (background dot in normal display). Column outputs (Column 0~63) of the...