Summit ™ T3-16 Analyzer for PCI Express® link width and link speed. Lane swizzling allows maximum flexibility to accommodate specialized or unique board layouts for MidBus connections. All events on links can be analyzed in both upstream and downstream directions. Key Benefits • Find Errors Fast – One button error check – Fast upload speed – Large trace memory – Powerful triggering/filtering • See and Understand the Traffic – Get useful information – More choices of data views – More ways to analyze data – Verification Script Engine included • Accurate Data Capture – 100% data capture at 8 GT/s on all lane widths up to x16 The Summit T3-16 Protocol Analyzer is a high-end analyzer that offers new features for Gen3 application development. While sharing application compatibility with the previous analyzer platforms, the Summit can record traces on SSC supported lanes at speeds of 2.5, 5 and 8 GT/s. Users acquainted with LeCroy’s multiple probing accessories will find the right probing required to do the job. The demands of debugging Gen3 speeds require new capability to reduce debugging time and accelerate time-to-market. The auto sense link feature allows tracing of the complete negotiation sequence for both • Most Extensive Probing Accessories in the PCIe Protocol Test Industry – Backward compatible with existing LeCroy Gen1 and Gen2 PCI Express probes The Summit T3-16 is LeCroy’s highest performance PCI Express analyzer, and offers advanced features such as: support for PCI Express Spec 3.0; data rates of 2.5 GT/s, 5 GT/s and 8 GT/s; full data capture on bidirectional lane widths of x1, x2, x4, x8 and x16; and 8 GB of trace memory. The product is ideal for high-performance protocol development for add-in boards, servers and workstations, and for customers currently working on PCIe Gen1 and Gen2 applications but with PCIe 3.0 on their roadmaps. Powerful displays allow for easy analysis of protocol traffic. The BitTracer™ software option records the bytes exactly as they come across the link, allowing debugging of PHY layer problems and combining the features of a logic analyzer format with a decoded protocol analyzer format. The Summit T3-16 for PCI Express utilizes the CATC Trace™ to assist users in analyzing how PCI Express components work together in diagnosing problems. The interface helps find errors fast by using the powerful triggering, filtering, and error reporting. View meaningful reports about performance and protocol behavior in real time, and post captured traffic. The CATC Trace is a powerful and intuitive expert software system, embedding detailed knowledge of the protocol hierarchy and intricacies as defined in the

SPECIFICATIONS AND ORDERING INFORMATION protocol specification. The CATC Trace utilizes a graphical display that has been optimized for fast and easy navigation through a captured traffic session. Users are alerted as violations are detected at all levels of the protocol layering, and can easily drill down to areas of interest or collapse and hide fields that are not relevant. Protocol data can be viewed in several ways from logical to chronological, and by events unique to PC Express. Know that your data is accurate through reliable and complete decodes of Transaction Layer Packets (TLPs), Data...