• Fast and Easy Debug for — Self-contained system offers easy connection — Custom probe design supports higher speed — Free trace viewer runs on • Comprehensive JEDEC — Detects over 65 JEDEC bus event & timing violations in real time — Extended recording time events vs. Logic Analyzer data for fast configuration — Dedicated trigger output to scope for Read/ Write • Innovative Displays Focused on Timing Analysis Timing Waveform views with the Bank State View bank and per DIMM slot — Real Time performance • Flexible, Scalable Platform — Monitor two slots of quad unbuffered DIMM types — Address...

Timing Navigation bar allows fast zoom-in analyze traces with custom markers State listing shows all command information including timing errors with the Bank State View Use event metrics to navigate to individual commands, addresses Traffic Summaries for Faster Analysis In addition to timing analysis, the Kibra 480 generates performance metrics that are displayed for read, write and power down operations. Bus metrics are tracked per bank, per rank, and per channel to provide insights into overall memory utilization. The error report shows protocol and timing violations with hyperlinks to the...

SPECIFICATIONS AND ORDERING INFORMATION Custom Sequential Event Triggering The Kibra 480 can specify custom triggers for any DDR command including MRS or Read/Write commands to a specific physical address. With the sequential triggering, the analyzer can wait for any two command/control states in sequence including any combination of high/low signaling. Optionally add a timer within the sequence to specify a timeout condition or re-arm the analyzer. Filtering of NOP & Deselect commands is available to selectively capture the most important operations. There's also a low-latency trigger- out that...