TELEDYNE LECROY

• Fast and Easy DDR3 Debug — Self-contained system — Fast & easy setup — Impedance matched Interposer probing • Comprehensive JEDEC & timing violations specific addresses • Innovative Displays Focused on Timing Analysis Timing Waveform displays — View Command metrics Flexible, Scalable Platform Extended recording unbuffered DIMM types — Address multi-channel cascading analyzers — CrossSync™ allows synchronized views with other serial busses Teledyne LeCroy Kibra™ 380 The Teledyne LeCroy Kibra 380 is a stand-alone DDR3 protocol analyzer that provides comprehensive DDR3 bus and JEDEC timing analysis....

Accurate wave-form display of all physical address attributes Timing Navigation bar allows fast zoom-in flexible timing State listing timing errors analyze traces with custom markers timing view Use event metrics to navigate to individual commands, addresses Traffic Summaries for Faster Analysis In addition to timing analysis, the Kibra 380 generates performance metrics that are displayed for read, write and power down operations. Bus metrics are tracked per bank, per rank, and per channel to provide insights into overall memory utilization. The error report shows protocol and timing violations...

SPECIFICATION AND ORDERING INFORMATION Trigger Out On Read / Write Operations The Teledyne LeCroy system features real-time trigger-out for Read / Write operations (WE). This dedicated, low latency SMA trigger out uses DQ/DQS relationships to distinguish Read / Write operations on the bus. Separating complex DQ signaling makes it easier to perform electrical layer characterization with an oscilloscope. The Read/Write Trigger can further specify Rank, Bank, Row and Column to isolate problematic operations. Analyzer System Specifications Host Minimum CPU Required is Intel Core 2 Duo Family Requirements...