Teledyne LeCroy offers a full line of DDR test solutions for system bring-up, debug, performance analysis, and compliance. The DDR Debug Toolkit is a unique and flexible tool for analyzing all aspects of the physical layer design. The HDA125 enables advanced command triggering and sophisticated, searchable bus state viewing. JEDEC compliance testing is supported on the physical layer with the QualiPHY compliance package and on the protocol layer with the Kibra compliance analyzer. TELEDYNE LECROY Everywhereyoulook" Key Features Test support for the entire DDR design cycle Support for DDR2/3/4 and LPDDR2/3 Physical Layer Debug Toolkit — Test, debug, and analysis tools for the entire DDR design cycle — Eye Diagrams with mask testing — Flexible DDR Measurements Physical Layer Compliance — JEDEC clock, electrical and timing compliance tests — Automatic reporting — Stop-on-test debug feature High-speed Digital Analyzer — Acquire and analyze DDR command bus signals — 12.5 GS/s digital acquisition — Unique QuickLink probing architecture Protocol Compliance and Debug — Quick and easy setup — Triggering for 50+ JEDEC Timing Violations — JEDEC protocol compliance Physical Layer DDR Toolkit The DDR Debug Toolkit provides test, debug, and analysis tools for the entire DDR design cycle. Unique DDR analysis capabilities provide automatic Read and Write burst separation, bursted data jitter analysis, and DDR-specific measurement parameters. All this DDR analysis can be performed simultaneously over four different measurement views. Physical Layer Compliance The QualiPHY DDR packages perform all of the clock, electrical and timing tests per the JEDEC standards. Upon completion of each test run a report is generated which contains pass/fail results as well as fully annotated screenshots of the worst case measurement. High-speed Digital Analyzer The HDA125 turns your Teledyne LeCroy oscilloscope into the highest-performance, most flexible mixed-signal solution for DDR debug and evaluation. With 12.5 GS/s digital sampling rate on 18 input channels and the revolutionary QuickLink probing solution, validation of DDR interfaces has never been simpler or more comprehensive. Protocol Compliance and Debug A combination of quick and easy hardware setup and immediate feedback on violations allows users to quickly validate JEDEC timing compliance or swiftly identify problem areas with their memory system. Capturing the Command Address and Control bus, the Kibra 480 can quickly identify timing issues associated with the JEDEC defined speed bins.

Successful development of new DDR products requires a coordinated test program to cover all aspects of the DDR design cycle. During system bring-up it is essential to perform functional testing which involves monitoring traffic on the protocol level and verifying eye diagrams and setup and hold time measurements on the physical layer. As the design matures, signal integrity analysis becomes crucial to perform optimization and system tuning to maximize system margin. Finally, no design is complete without testing compliance to JEDEC requirements on both the physical and protocol layers. It is...

Challenges with Adopting Next Generation DDR DDR standards are developed by the Joint Electron Device Engineering Council (JEDEC) but the responsibility for adhering to these standards is left up to the designer. Not all DDR implementations will require testing to the JEDEC standard but almost all will require some level of testing to ensure reliable data transfer. The adoption of each new generation of DDR seemingly offers double the maximum data transfer rate with a lower power consumption, leaving less design margin and presenting increasingly difficult design and test challenges. Having the...

Key Features Automated Read/Write burst separation Simultaneous analysis of four different measurement views View up to 10 eye diagrams with mask testing and eye measurements Searchable Bus State views with intuitive color-coded overlay Command bus based triggering Perform jitter analysis for root cause analysis Quickly configure DDR-specific measurements Analyze specific regions of bursts with configurable qualifiers Support for DDR2/3/4 and LPDDR2/3 Select standard and custom speed grades Most oscilloscope-based DDR physical layer test tools are targeted exclusively at JEDEC compliance testing,...

The bursted nature of DDR signals makes it very different than most serial data communication standards. As a result, the traditional oscilloscope-based methods and algorithms for measuring jitter and analyzing system performance are not capable of measuring DDR signals. The DDR Debug Toolkit uses jitter algorithms which have been tailored for bursted DDR signals. Built-in DDR measurement parameters provide various JEDEC compliance measurements which are important for debugging and characterizing DDR systems. Four Measurement Views When configuring a measurement, each view can be independently...

Key Features Complete test coverage as described by JEDEC specifications Supports all standard and custom speed grades Separate bursts using DQ-DQS phase or DDR command bus Statistically relevant results achieve measurement confidence Report generation with pass/fail results and fully annotated worst case measurement screenshot DDR Debug Toolkit integration for easy and flexible debug Maximize signal integrity with deembedding and Virtual Probing Leverages industry leading serial data algorithms for jitter breakdown and eye rendering Accurate Burst Separation Read and Write bursts can be separated...

QualiPHY QualiPHY is designed to reduce the time, effort, and specialized ­ knowledge needed to perform compliance testing on high-speed serial buses. Guides the user through each test setup P erforms each measurement in accordance with the relevant ­ test procedure C ompares each measured value with the applicable ­specification limits F ully documents all results Q ualiPHY helps the user perform testing the right way — every time Compliance Reports contain all of the tested values, the specific test limits and screen captures. Compliance Reports can be ­ reated as HTML, PDF or XML. c Clock...