SB16C554A, Quad-UART Asynchronous Communications Element SB16C554AQuadruple Universal Asynchronous Receiver and Transmitter SB16C554A is an enhanced quadruple version of the 16C550 UART(Universal Asynchronous Receiver Transmitter). Each channel can be put into FIFO mode to relieve the CPU of excessive software overhead. In this mode, internal FIFOs are activated and 16 bytes plus 3bits of error data per byte can be stored in both receive and transmit modes. Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. The Status information includes the type and condition of the transfer operations being performed by the UART as well as any error conditions such as parity, overrun, framing and break interrupt. SB16C554A has complete MODEM-control capability and an interrupt system that can be programmed to the user's requirement, minimizing the computing required to handle the communication links. ■ SB16C554A Features IORMOW# < RESET A(2:0) CS#(3:0) INT(3:0) >1 TXRDYffRXRDY# ^

SB16C554A, Quad-UART Asynchronous Communications Element ■ SB16C554A Features - Integrated Four Improved SB16C550A UART - In the FIFO mode, Each channel's transmitter and receiver is buffered with 16-byte FIFO to reduce the number of interrupts to CPU. - Adds or deletes standard asynchronous communication bits(start, stop, parity) to or from the serial data. - Holding Register and Shift Register eliminate needs for the precise synchronization between the CPU and serial data. - Independently controlled transmit, receive, line status and data interrupts. - Programmable Baud Rate Generators which...