• Automotive: High defect coverage, optimal in-system test time and coverage, power-on/off & IST controller, ASIL quality requirements.
• AI/Hyperscaler: Scalable test architecture, RTL-based hierarchical test, high identical core compression, physical design flexibility.
• 5G and Consumer: Advanced compression, RTL-based hierarchical test, maximize block DFT reuse, fast runtime & iterations.

Synopsys TestMAX is part of the Synopsys.ai hyperconvergent EDA stack, addressing silicon design, test, and analytics challenges in advanced technologies.

• Turn-around time
• Cost and quality
• Scalability
• Engineering resources

• TestMAX Manager: Comprehensive RTL editing, hierarchical pattern porting, and a common interface for all DFT tools.
• TestMAX Advisor: DFT violation checking, ATPG coverage estimation, and test points selection to shorten test implementation time.
• TestMAX DFT: High test time and data reduction, patented compression technologies, and RTL generation with TestMAX Manager.
• TestMAX ATPG: Automatic test pattern generation for faster runtime, reduced memory bottlenecks, and consistent results.
• TestMAX XLBIST: Supports standard and high X-tolerance architectures, addressing ISO 26262 automotive functional safety.
• TestMAX ALE: Enables HSIO’s with Synopsys HSAT IP for high bandwidth test, simplifying ATE pin electronics.
• TestMAX Vtran: Translates ATPG patterns into various ATE formats, streamlining production test flow.
• TestMAX Diagnosis: Quickly finds silicon defect candidates, supports CAFM, and isolates systemic defects.
• SMS IP: Supports various memory types, offering complete test, repair, debug, and diagnostics.
• SHS IP: Automated hierarchical test and integration of all IP/Cores on SoC.
• TSO.ai: Industry-first Test-AI technology that scales to available compute and minimizes pattern count.

Synopsys provides expert global support and services for all TestMAX products, including compliance and customizations.