Broad IP Portfolio Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys’ extensive investment in IP quality, comprehensive technical support and robust IP...

UPLI Interface Process Technologies Endpoint, Root Port, Dual Mode, Switch Device Router, Host Router Host, Dual Role, DisplayPort TX, HDCP ESM, DSC Host, Device, Dual Role Host, Dual-Role, DisplayPort TX, HDCP ESM, DSC Host, Device, Dual-Role Host, Device, Dual-Role Host, Device, Dual-Role Host, Device, Dual-Role Host, Device, Dual-Role Host, Device, Dual-Role

Embedded Flash

*Available in Consumer and Automotive

*Available in Consumer and Automotive

Silicon Lifecycle Management (SLM) IP * Automotive Grade

Synopsys' ARC® Processor IP is a portfolio of CPUs, DSPs and NPUs that SoC designers can optimize for a wide range of uses, from deeply embedded to high-performance host applications, in a variety of market segments. The portfolio includes 32- and 64-bit ARC-V™ Processor IP based on the open-standard RISC-V ISA. ARC processors offer a high degree of configurability that enables designers to tailor each processor instance to meet their specific performance, power and area requirements. ARC processors are also extensible, allowing designers to customize their implementation with proprietary instructions...

Vision Processors

With IP Accelerated, Synopsys has augmented its broad portfolio of silicon-proven Synopsys IP with SoC architecture design support, IP subsystems, signal integrity/power integrity analysis and IP hardening, and comprehensive silicon bring-up support to accelerate your product development cycle. IP Subsystems support many protocols and deliveribles for IP integration including configuration scripts, test environment, test scripts, linting, CDC checks, RDC checks, synthesis scripts and implementation scripts. The subsystems also include AMBA or native bus, clock management, reset, DMA, interrupts,...

Multi-protocol Support Floor Planning Scan Insertion Power Grid Skew Balancing Bump Assignment DDR/LPDDR HBM2E / HBM3 UCIe, PCIe Signal/Power Integrity Analysis Supported IP Multi-protocol Support Floorplan Review Pre/Post Layout Analysis Decap Cell Size/Placement Power Impedance Simulations Timing Budget Analysis Signal Quality PVT Corner Analysis Full Report DDR/LPDDR HBM2E / HBM3 UCIe HBI PCIe MIPI Ethernet For more information on Synopsys IP, visit synopsys.com/ip. ©2025 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries....