High-performance physical verification solution delivers up to 2X faster physical signoff Overview Synopsys' IC Validator physical verification is a comprehensive signoff solution improving productivity for customers at all process nodes from mature to advanced. The IC Validator tool offers the industry's best distributed processing scalability to over 2000 CPU cores. The tool's performance and scalability has enabled some of the industry's largest reticle limit chips with billions of transistors, same day design rule checking (DRC), layout versus schematic (LVS), and dummy fill turnaround time. IC Validator physical verification is seamlessly integrated with Fusion Compiler™ RTL-to-GDSII solution and IC Compiler® II place and route system in the Fusion Design Platform. This integrated physical verification Fusion Technology™ accelerates design closure for manufacturing by enabling independent signoff-quality analysis and automatic repair within the implementation environment. • Industry leading physical verification performance enabled by distributed processing scalability past 2000 CPU cores • Cloud-ready physical signoff, certified by TSMC • Explorer technology for 5X faster DRC verification during SoC integration • Elastic CPU management adds and removes CPUs dynamically • Physical Verification Fusion within place and route enabling automatic DRC repair, timing aware FILL, and engineering change order (ECO) capabilities • LVS-aware simulation based short-finder • Integration with StarRC™ parasitic extraction, Custom Compiler™ full-custom design environment, and other third-party layout tools for increased designer productivity • Live DRC for signoff quality on-the-fly DRC checking within full custom layout design tools • Programmable Electrical Rule Checks (PERC) for customized checking for EOS/ESD/ERC rules • Signoff certified at leading foundries with the broadest qualification and runset availability

Leading Performance and Scalability IC Validator is architected for massively parallel distributed processing. IC Validator enables excellent scalability to 2000+ CPU cores. The built-in memory awareness keeps jobs within machine memory resource limits. IC Validator’s elastic CPU management adds and removes CPUs dynamically. Intelligent file management balances disk, memory and speed up multi-host environment. IC Validator is a cloud ready physical signoff solution. Its secure, scalable and certified by TSMC for signoff. Figure 1: IC Validator scalability IC Validator’s smart load sharing technology...

Start run with available CPU’s Add CPU’s to existing run as they come online Add more CPU’s to existing run to improve runtime Release CPU’s when determined no longer required by run Figure 3: Elastic CPU management Explorer DRC IC Validator’s innovative Explorer DRC technology is a paradigm shift in how very big, very dirt designs are handled from the early SoC integration stages, to final full chip DRC signoff. For design verification during SoC integration, Explorer DRC offers 5X faster runtime with 5X fewer CPUs. Additionally, Heatmap based debugging enables order-of-magnitude debugging speedup....

Heatmap debugging with Explorer DRC allows designers to debug billions of DRC violations very quickly. Users are shown either in supported layout environments or directly in IC Validator - Visualization User Environment (VUE) heatmap details that enable designers to quickly pinpoint fundamental design flaws. DRC Heatmap provides designers with DRC error type, error density, error location, and error congestion. Macro Overlap FILL-Signal Alignment Issue Figure 6: DRC heatmap highlighting error locations, density, and severity DRC Typical Advanced Node DRC Super Cycle Figure 7: Explorer DRC accelerates...

IC Validator’s seamless integration with Fusion Compiler and IC Compiler II enables an innovative layout auto-correction interface, which identifies DRC violations, including DPT decomposition violations and initiates automatic repairs. The corrections are applied by Fusion Compiler and IC Compiler II to alleviate DRC and DPT errors, and then validated with signoff foundry runsets using IC Validator Physical verification. Fusion integration makes it possible to maintain hotspot-free designs throughout implementation, further eliminating iterations. Timing Aware Fill At advanced nodes, fill insertion...

Synopsys’ IC Validator is the proven high performance and comprehensive signoff physical verification solution. Trusted by leading semiconductor companies and used in hundreds of production designs, IC Validator offers a physical verification tool suite including DRC, LVS, Programmable Electrical Rule Checks (PERC), dummy fill, and Design For Manufacturing (DFM) capabilities. Foundry Qualification Comprehensive foundry qualification is a necessary component of any successful physical verification solution. IC Validator is signoff certified by all major foundries. IC Validator is actively in production...

PERC IC Validator PERC is a reliability verification solution that enables customized checking for EOS/ESD/ERC rules. Programmable Electrical Rule Checks (PERC) supports checking of Netlist Domain Checks (NDC), Mixed-Mode Checks (MMC), also Current Density (CD), and Point-to-Point Resistance (P2P). IC Validator PERC technology provides fast performance, scalability and intuitive debugging for reliability verification. PERC leverages the hierarchical processing power of IC Validator to provide a unique chip level solution. Key capabilities include: • Current density checking with StarRC extraction...

Full Custom Frameworks IC Validator supports full interoperability for job execution, layout error shape probing, schematic cross probing with Visualization User Environment (VUE) within Synopsys Custom Compiler™ and supported third party solutions. IC Validator with StarRC for post layout extraction will write a logical extracted view to Openaccess. IC Validator LVS provides the ideal layout extracted netlist used by StarRC for the Custom Compiler integrated CustomSim-RA EM/IR reliability analysis flow. Figure 15: Execution and debug from with custom design tools Layout Visualization: Integration...