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STA8058 GPS multi-chip module

STA8058 GPS multi-chip module
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Data Brief For further information contact your local STMicroelectronics sales office. March 2009 Rev 2 1/14 14 STA8058 TESEO™ high performance GPS multichip module (MCM) Features ¡ GPS multichip module: – STA2058 TESEO Baseband – STA5620 RF Front-end ¡ Complete embedded memory system: – Flash 256 KB + 16 Kbytes – RAM 64 Kbytes. ¡ 66-MHz ARM7TDMI 32 bit processor ¡ High performance GPS engine (HPGPS) ¡ SBAS (WAAS and EGNOS) supported ¡ Sensitivity (-146 dBm acquisition, -159 dBm tracking) ¡ Time to first fix (1 s reacquisition, 2.5 s hot start, 34 s warm start, 39 s cold start) ¡ Accuracy (2 m autonomous) ¡ Extensive GPS receiver interfaces: 32 GPIOs, 4 UARTs, 2 SPIs, 2 I2Cs, 1CANs 2.0, 1 USB 1.1, 1 HDLC and 4 channels ADC ¡ Compatible with L1 signal (C/A code) ¡ ST proprietary technology – CMOS Flash embebbed technology for STA2058 – BiCMOS Sige technology for STA5620 ¡ LFBGA104 lead-free package ¡ -40 °C to 85 °C operating temperature range Evaluation kits ¡ STA8058 module reference designs (17x19 mm and 25x25 mm) ¡ Evaluation board hosting STA8058 module Description STA8058 TESEO MCM is a fully embedded GPS engine integrating STA2058 TESEO baseband. and STA5620 RF front-end. The embedded Flash memory enables the equipment manufacturer to load the entire GPS software (including tracking, acquisition, navigation and data output) after customising its interfaces to his needs. A standard GPS library is available from ST. By combining the ARM7TDMI microcontroller core with on-chip Flash/RAM, 16-channel GPS correlator DSP, RF Front-end and an extensive range of interfaces on single package solution, the STA8058 provides a highly-flexible and costeffective solution for GPS applications. LFBGA104 (7x11x1.4 mm) Table 1. Device summary Order Code Package Packing Automotive Grade STA8058 LFBGA104 (7x11x1.4mm) Tray No STA8058TR LFBGA104 (7x11x1.4mm) Tape and reel No STA8058A LFBGA104 (7x11x1.4mm) Tray Yes STA8058ATR LFBGA104 (7x11x1.4mm) Tape and reel Yes www.st.com

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Contents STA8058 2/14 Contents 1 Features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 LFBGA104 ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Power supply pins...

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STA8058 Features summary 3/14 1 Features summary œ ARM7TDMI 16/32 bit RISC CPU based host microcontroller running at a frequency up to 66 MHz. œ Complete Embedded Memory System: – Flash 256 Kbytes + 16 Kbytes (100 KB erasing/programming cycles) – RAM 64 Kbytes. œ 16 channel High performance GPS correlation DSP. œ ST propietary technology: – CMOS Flash embedded technology for baseband – BiCMOS Sige for radio front-end œ SBAS (WAAS and EGNOS) supported. œ -40 °C to 85 °C operating temperature range. œ 104-pin LFBGA104 package. œ Power supply: – 3.0 V to 3.6 V operating supply range for...

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Features summary STA8058 4/14 œ Two I2C interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 KHz), 7/10 bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2 x SPI + 1 x I2C or 1 x SPI + 2 x I2C may be used at a time. œ Enhanced interrupt controller supports 32 interrupt vectors, independently maskable, with interrupt vector table for faster response and 16 priority levels, software programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ. œ Wake-up unit allows exiting from powerdown modes by detection of...

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STA8058 Pin description 5/14 2 Pin description 2.1 Logic symbol Figure 1. STA8058 TESEO MCM symbol AVSS CK SPI (DI,DO,CS, CLK) JTDI JTDO JTCK JTMS RSTINn JTRSTn RF_IN BOOTEN V18BKP V18 [2] V33 [7] V27 [8] Xtal (IN,Out,Clk) AVDD Power Clock & Reset JTAG Port TESEO GPSCLK GPSDAT Pads VSS [10] VSSRF [11] RF Pads Sign GPS_CLK Enable (Chip,RF) Mode IF_TEST AGC_CNTR P0.[15:0] P1.[15:0] RTCXTI RTCXTO USBDP USBDN WAKEUP GeneraI Purpose I/O RTC USB Pads & WKUP Pads nSTDBY_I MCM

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Pin description STA8058 6/14 2.2 System block diagram Figure 2. STA8058 TESEO baseband block diagram APB BRIDGE3 5 DP 256K Flash ARM7TD MI 64KRAM STC (JTAG) ARM7 Native BUS INTERRUPT CONTR. 12-bit ADC TIMER0 WATCH DOG Fully Prog. I/O PORTS 5 DP UART0 4 AF APB BRIDGE2 1 DP 2 AF 32 IO 4 AF TIMER1 RTC 2 DP UART1 UART2 UART3 2 AF 2 AF 2 AF 2 AF HPGPS 16-ch. correlator + Emerald DSP [USB] 3 DP HDLC 3 AF 16 AF Wakeup OSCILL [CAN] 2 AF 3 DP VREG RCCU PLL I2C0 2 AF I2C1 2 AF APB BUS APB BRIDGE1 SPI0 4 AF APB BUS 2 AF TIMER2 4 AF TIMER3 3 DP SPI1 4 AF

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STA8058 Pin description 7/14 Figure 3. STA5620 RF front-end SPI Interface CP CMOS Drivers 2 bits Combiner RFA Buffer Xtal Osc PFD / N IR Mixer Polyphase Filter IF filter GPS_CLK / 48 0° 90° XTAL_CLK RF_EN AGC_CTRL RF_IN MAG SIGN / 2 / R SPI_CS/ SPI_CLK SPI_DI SPI_DO MODE sign mag gps_clk gce xce ADC XO XI TEST_EN2 hce lo48_clk gps_clk sample_mode (1:0) LO96 Variable Xtal gce & rfe enabled by rfe & speci fic enables Reset Generator reset IF_TEST TEST_EN1 test_clk sign mag AGC if_out_en CHIP_EN xtal_clk xtal_clk mag Test TEST_CLK Logic

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Pin description STA8058 8/14 Figure 4. STA8058 TESEO MCM block diagram RF_IN Sign GPS_Dat CHIP_EN SAW Filter AGC_CNTR RF_EN V27_RF [5] LNA JTDI,JTCK,JTMS,JTRSTn,JTDO STA8058 Teseo MCM STA5620 RF Front-End STA2058 Baseband SPI_DI SPI_DO SPI_CLK S1_MOSI S1_MISO S1_SCLK GPS_CLK CK XTAL_IN MODE IF_TEST V27_PLL[4] VSSRF [10] Wake_Up RTCXTO RTCXTI 3 Timers [9], ADC[4] The two dice must be interconnected eachother at boarld leve SPI[4], I2C[3], 3 UARTS [6] USB[3], CAN[2], HDLC[3] P1.8/PPS NRSTIN P1.9/PRN BOOT0, BOOT1, BOOTEN NSTDBY_IN V33 [4] V18[2] VSS [4] V33IO_PLL V33_REG_BKP AVDD V18BKP...

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