March 2010 Doc ID 16482 Rev 2 1/72 1 SPEAr310 Embedded MPU with ARM926 core, flexible memory support, extended set of powerful connectivity features Features ¡ ARM926EJ-S 333 MHz core ¡ High-performance 8-channel DMA ¡ Dynamic power-saving features ¡ Configurable peripheral functions multiplexed on 102 shared I/Os ¡ Memory: – 32 KB ROM and 8 KB internal SRAM – LPDDR-333/DDR2-666 external memory interface – Serial Flash Memory interface (SMI) – Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting NAND Flash – External memory interface (EMI) up to 32- bit data bus width, supporting NOR Flash and FPGAs ¡ Connectivity – 2 x USB 2.0 Host – USB 2.0 Device – 1 x fast Ethernet MII port – 4 x fast Ethernet SMII ports – 1 x SSP Synchronous serial peripheral (SPI, Microwire or TI protocol) with 4 chip selects – 1 x I2C – 1 x fast IrDA interface – 6 x UART interface – 1x TDM/E1 HDLC interface with 128/32 timeslots per frame respectively – 2x RS485 HDLC ports ¡ Security – C3 Cryptographic accelerator ¡ Miscellaneous functions – Integrated real time clock, watchdog, and system controller – 8-channel 10-bit ADC, 1 Msps – JPEG CODEC accelerator – Six 16-bit general purpose timers with programmable prescaler, 4 capture inputs – Up to 102 GPIOs with interrupt capability Applications The SPEAr310 embedded MPU is configurable for a range of telecom and networking applications such as: ¡ Routers, switches and gateways ¡ Remote apparatus control ¡ Metering concentrators Table 1. Device summary Order code Temp range, °C Package Packing SPEAR310-2 -40 to 85 LFBGA289 (15x15 mm, pitch 0.8 mm) Tray LFBGA289 (15 x 15 x 1.7 mm) www.st.com

Contents SPEAr310 2/72 Doc ID 16482 Rev 2 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 CPU ARM 926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Power...

SPEAr310 Contents Doc ID 16482 Rev 2 3/72 2.19 USB2 device controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.20 Cryptographic co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.21 JPEG CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 Required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 Dedicated pins . . . . ....

Contents SPEAr310 4/72 Doc ID 16482 Rev 2 6.3 FSMC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3.1 8-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.2 16-bit NAND Flash configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4 Ether MAC 10/100 Mbps timing characteristics . . . . . . . . . . . . . . . . . . . . 57 6.4.1 MII transmit timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4.2 MII receive timing specifications . . . . . . ....

SPEAr310 List of tables Doc ID 16482 Rev 2 5/72 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Master clock, RTC, Reset and 3.3 V comparator pin descriptions . . . . . . . . . . . . . . . . . . . 26 Table 3. Power supply pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4. Debug pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 5....

List of tables SPEAr310 6/72 Doc ID 16482 Rev 2 Table 47. UART receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 48. LFBGA289 (15 x 15 x 1.7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 49. Thermal resistance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 50. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

SPEAr310 List of figures Doc ID 16482 Rev 2 7/72 List of figures Figure 1. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 2. Typical system architecture using SPEAr310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. Clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. Typical SMII system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....

Description SPEAr310 8/72 Doc ID 16482 Rev 2 1 Description The SPEAr310 is a member of the SPEAr family of embedded MPUs, optimized for telecom applications. It is based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in applications where high computation performance is required. In addition, SPEAr310 has an MMU that allows virtual memory management -- making the system compliant with advanced operating systems, like Linux. It also offers 16 KB of data cache, 16 KB of instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations. A full set of peripherals...