RHF1201 Rad-hard 12-bit 50 Msps A/D converter Features Failure immune (SEFI) and latchup immune (SEL) up to 120 MeV-cm2/mg at 2.7 V and 125° C Hermetic package Wide sampling range OptimwattTM adaptive power: 44 mW at 0.5 Msps, 100 mW at 50 Msps Optimized for 2 Vpp differential input Built-in reference voltage with external bias capability Digital communication satellites Space data acquisition systems Aerospace instrumentation Nuclear and high-energy physics The upper metallic lid is not electrically connected to any pins, nor to the IC die inside the package. Description The RHF1201 is a 12-bit 50 Msps sampling frequency analog-to-digital converter that uses pure (ELDRS-free) CMOS 0.25 µm technology combining high performance, radiation robustness and very low power consumption. The device is based on a pipeline structure and digital error correction to provide excellent static linearity. Specifically designed to optimize the speed power consumption ratio, the RHF1201 integrates a proprietary track-and-hold structure making it ideal for IF-sampling applications up to 150 MHz. A voltage reference network is integrated in the circuit to simplify the design and minimize external components. A tri-state capability is available on the outputs to allow common bus sharing. Output data can be coded in two different formats. A Data Ready signal, raised when the data is valid on the output, can be used for synchronization purposes. Quality level Engineering model Lead Packing finish Strip pack Strip pack 1. Contact your ST sales office for information about the specific conditions for products in die form and for information about SMD packages.

Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 9 Electrical characteristics (unchanged after 300 kRad) . . . . . . . . . . . . 10 7.1 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power consumption optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1

Block diagram Block diagram Figure 1. Block diagram Sequencer-phase shifting Digital data correction VCCBI VCCBE

Figure 2. Pin connections (top view)

Digital buffer ground Slew rate control input Digital buffer ground Output Enable input Digital buffer power supply Data Format Select input Analog power supply Analog power supply Out-of-range output Analog ground Most significant bit output Analog bias current input Digital output Digital output Bottom voltage reference Digital output Analog ground Digital output Analog input Digital output Analog ground Digital output Inverted analog input Digital output Analog ground Digital output Input common mode Digital output Analog ground Digital output Analog power supply Least significant bit output...

Equivalent circuits Equivalent circuits Analog inputs Output buffers VCCBE Clock input Data format input Slew rate control input Output enable input

Equivalent circuits Figure 9. VREFP and INCM input AVCC INCM Input impedance = 50 Ω VREFP Input impedance = 39 Ω Figure 10. VREFM input AVCC VREFM High input impedance

Timing characteristics Timing characteristics Table 3. Timing table Test conditions Data output delay (fall of clock to data valid) Data pipeline delay (2) Data ready rising edge delay Duty cycle = 50% after data change (3) Falling edge of OEB to digital output valid data Rising edge of OEB to digital output tri-state 1. See Figure 34. 2. Guaranteed by design. 3. Tdr is linked to the duty cycle, conditioned by the duration of the low level of DR signal. 4. See Figure 35 and Figure 36. Figure 11. Timing diagram N+2 Data output The input signal is sampled on the rising edge of the clock while the...

Absolute maximum ratings and operating conditions Absolute maximum ratings and operating conditions Table 4. Absolute maximum ratings Analog supply voltage Digital supply voltage Digital buffer supply voltage Digital buffer supply voltage Analog inputs: bottom limit −> top limit External references: bottom limit −> top limit VIN VINB VREFP VINCM IDout Digital output current Storage temperature Thermal resistance junction to case Thermal resistance junction to ambient 1. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩ resistor between...

Electrical characteristics (unchanged after 300 kRad) Electrical characteristics (unchanged after 300 kRad) Unless otherwise specified, the test conditions in the following tables are: AVCC = DVCC = VCCBI = VCCBE = 2.5 V, FS = 50 Msps, differential input configuration, Fin = 15 MHz, VREFP = internal, VREFM = 0 V, Tamb = 25° C. Analog inputs Symbol VIN-VINB Test conditions Full-scale input differential voltage (FS)(2) Effective resolution bandwidth Input resistance Input capacitance 1. See Chapter 8: Definitions of specified parameters on page 29 for more information. 2. Optimized differential...

Electrical characteristics (unchanged after 300 kRad) Digital inputs and outputs Test conditions Clock threshold Clock amplitude (DC component = 1.25 V) Square clock DVCC = 2.5 V High impedance leakage current Dynamic characteristics Parameter Test conditions Spurious free dynamic range Signal to noise ratio Total harmonics distortion F = 260 kHz Fs = 2 MHz Rpol = 200 k Ω each power supply at 2.5 V decoupled by 10 µF//470 nF Signal to noise and distortion ratio Effective number of bits Power supply rejection ratio

Electrical characteristics (unchanged after 300 kRad) Figure 12. Differential input configuration input signal Figure 13. ENOB vs. diff. input, square clock Figure 14. SINAD vs. diff. input, square clock Differential input Square clock Internal INCM and VREFP Differential input Square clock Internal INCM and VREFP Figure 15. THD vs. diff. input, square clock Figure 16. SNR vs. diff. input, square clock Differential input Square clock Internal INCM and VREFP Differential input Square clock Internal INCM and VREFP