HD1750FX HIGH VOLTAGE NPN POWER TRANSISTOR FOR HIGH DEFINITION AND NEW SUPER-SLIM CRT DISPLAYS ■ STATE-OF-THE-ART TECHNOLOGY: DIFFUSED COLLECTOR "ENHANCED GENERATION" EHVS1 WIDER RANGE OF OPTIMUM DRIVE CONDITIONS LESS SENSITIVE TO OPERATING TEMPERATURE VARIATION FULLY INSULATED POWER PACKAGE U.L. COMPLIANT HORIZONTAL DEFLECTION OUTPUT FOR DIGITAL TV, HDTV AND HIGH-END MONITORS Figure 2: Internal Schematic Diagram DESCRIPTION The device is manufactured using Diffused Collector in Planar technology adopting "Enhance High Voltage Structure" (EHVS1) developed to fit High-Definition CRT displays. The new HD product series show improved silicon efficiency bringing updated performance to the Horizontal Deflection stage. Table 1: Order Codes Part Number

HD1750FX Table 2: Absolute Maximum Ratings Symbol Collector-Emitter Voltage (IB= 0) Emitter-Base Voltage (IC= 0) VEBO IC ICM IB IBM Ptot Vins Tstg TJ Collector Current Collector Peak Current (tp < 5ms) Base Current Base Peak Current (tp < 5ms) Total Dissipation at TC = 25 C Insulation Withstand Voltage (RMS) from All Three Leads to External Heatsink Storage Temperature Max. Operating Junction Temperature Table 3: Thermal Data Rthj-case Thermal Resistance Junction-Case Table 4: Electrical Characteristics (Tcase = 25 oC unless otherwise specified) Symbol ICES Test Conditions Emitter Cut-off Current...

HD1750FX Figure 3: Safe Operating Area Figure 6: Derating Curve Figure 4: Output Chatacterisctics Figure 7: Reverse Biased SOA Figure 5: DC Current Gain Figure 8: DC Current Gain

HD1750FX Figure 9: Collector-Emitter Saturation Voltage Figure 12: Base-Emitter Saturation Voltage Figure 10: Power Losses Figure 13: Power Losses Figure 11: Inductive Load Switching Time Figure 14: Inductive Load Switching Time

HD1750FX Figure 15: Power Losses and Inductive Load Switching Test Circuit Figure 16: Reverse Biased Safe Operating Area Test Circuit

HD1750FX Figure 5: Revision History Release Date Change Designator Initial Release. New hFE value in table 4

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