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FDA903U

Product catalog summary

Overview: The FDA903U is a 45 W class D digital input automotive power amplifier designed for car audio and telematics applications. It features integrated D/A conversion, ILoad current monitoring, and operates over a wide voltage range.

Key Features:

AEC-Q100 qualified for automotive applications.
Integrated 108 dB D/A conversion with I2S and TDM digital input support.
Wide input sampling frequencies: 44.1 kHz to 192 kHz.
Operates on a supply range from 3.3 to 18 V, suitable for various automotive applications.
Includes MOSFET power outputs with high output power capability.
Power limiting function configurable via I2C.
Comprehensive diagnostics including short circuit, thermal warnings, and DC offset detection.
Integrated thermal, short circuit, and ESD protections.

Specifications:

Output power: 1 x 25 W /4 Ω @ 14.4 V, 1 kHz THD = 1% and 1 x 30 W /4 Ω @ 14.4 V, 1 kHz THD = 10%.
Supports 2 Ω loads driving.
Legacy mode available for operation without I2C.

Diagnostics and Protection:

I2C bus diagnostics for short to VCC/GND, short load, and open load detection.
Four thermal warnings and clipping detector.
Integrated thermal protection and 'hot spot' detection.

Additional Features:

Configurable power limiting function.
Real-time load current monitoring with I2C control.
Noise gating and dither PWM for improved audio performance.

Interface and Control:

Full I2C bus driving capability with 3.3/1.8 V support.
Multiple TDM modes (4/8/16CH) for flexible audio input configurations.
Comprehensive I2C and I2S bus interfaces for control and data communication.

Package Information: The FDA903U is available in a PowerSSO-36 package with an exposed pad for enhanced thermal performance.

Electrical Characteristics: The document outlines various electrical characteristics of the FDA903U, including I2C and I2S bus interfaces, control pin characteristics, clipping and offset detection, and current sensing. Key parameters such as clock frequency, voltage levels, and current limits are specified for both I2C and I2S interfaces. The document also details the conditions for high and low-level output voltages and the characteristics of enable pins.

Efficiency and Power Dissipation: Figures in the document illustrate efficiency and power dissipation under different conditions, such as varying supply voltages and load resistances. These figures help in understanding the performance of the FDA903U under different operational scenarios.

LC Filter Design: The document discusses the importance of the LC filter in a Class D amplifier, emphasizing the need for careful component selection to balance size, cost, and performance. It highlights the challenges posed by non-linear behavior of inductors and capacitors and the impact on Total Harmonic Distortion (THD).

Load Possibilities: The FDA903U supports various load configurations, including 2 Ω and 4 Ω loads, with specific voltage limits for each configuration.

Finite State Machine: The FDA903U features a finite state machine that manages amplifier functionality, allowing for different operational modes and I2C address configurations. The document details the transition between states such as Standby, Diagnostic, ECO-mode, MUTE, and PLAY, and the conditions that trigger these transitions.

Muting Function Architecture: The muting function in the FDA903U is achieved through a combination of analog and digital muting mechanisms. The document describes various mute command signals and their effects on the amplifier's output, including conditions for low battery, high voltage, thermal, and hardware mute.

Command Dependence: The document provides a table outlining the dependence of mute and unmute actions on different command signals, specifying when analog and digital muting is applied.

Muting Function Architecture: The document describes the muting function architecture of the FDA903U, highlighting the use of both Analog-Mute and Digital-Mute. The unmuting process begins when all mute commands exit the muting window, resetting the Start-Analog-Mute signal. The mixed mute approach combines Analog-Mute and Digital-Mute for robustness, especially when command signal variations last longer than the muting/unmuting time.

Hardware Mute Pin: The "HWMute" pin acts as a mute command for the channel, muting the device when low and playing when high. A pull-up current generator ensures the device plays if the pin is floating. An external pull-down open drain is needed to drive the Mute pin for hardware muting.

Power Limiter Function: An adjustable power limiting function protects small speakers by limiting the maximum power delivered to the load. This is achieved through input signal management, independent of supply voltage. The limitation is gradual to avoid impacting acoustic performance, with configurable thresholds via I2C.

Diagnostic Functions: The FDA903U includes diagnostic functions to detect faults such as short circuits, open loads, under/over voltage events, and more. Faults are stored in the I2C interface and can trigger interrupts. The DC diagnostic routine detects load connection status, while the short to Vcc/GND diagnostic identifies shorts. The open load in play detector checks for speaker detachment during play, using the audio signal itself for detection.

Open Load in Play Detector: This feature detects speaker detachment during play by evaluating the audio signal and output current. It processes the audio bandwidth up to 2kHz and requires the audio signal to exceed certain thresholds for valid detection.

Input and Output Offset Detectors: The input offset detector identifies offsets from the audio signal source, while the output voltage offset detector identifies voltage offsets on the output, generating a fault condition if persistent.

Output Voltage Offset Detector: The output voltage offset detector is designed to identify fault conditions by setting a flag on I2C bit DB0[3]. It resets when the fault is removed. This feature is active in both MUTE and PLAY states but should not be enabled when FBP and FBM pins are shorted with OUTP and OUTM pins. An alternative is the Output Current Offset Detector.

Output Current Offset Detector: This detector identifies current offsets by measuring the differential DC current through output pins. If the offset exceeds a set threshold, it communicates detection via I2C. The detection is a single-shot test controlled by I2C commands and can be initiated in MUTE or PLAY states.

PWM Pulse Skipping Detector: This feature detects PWM stage saturation by identifying skipped PWM commutations. It is enabled by setting IB5[5,4]='01' and provides output by enabling a pull-down on the CDDiag pin or setting a flag.

Thermal Protection: The device has multiple levels of thermal protection. The first level communicates temperature exceeding thresholds. The second level attenuates the output signal to reduce power dissipation. The third level shuts off the power stage if the temperature exceeds a critical value.

Watch-dog: An internal watch-dog can be enabled to send a muting command to the amplifier if a timeout occurs, which is reset by a new Word Select line edge.

Error Frame Check: This function checks the coherence of the clock line with the I2S protocol configuration and sets a flag if an error is detected.

Additional Features:

AM Operation Mode: Allows selection of PWM switching frequency to avoid EM interference.
Noise Gating: Reduces noise when output signal is at inaudible levels.
Dither PWM: Improves EMC performance by modulating the PWM period.
Real-Time Load Current Monitoring: Provides continuous load monitoring and diagnostic features.

I2S Bus Interface: The device receives audio signals through the I2S bus, supporting various sampling frequencies and data formats. It processes the first 24 most significant bits of a 32-bit data word. The interface requires proper configuration of I2C bits for correct operation.

Group Delay: The group delay of the FDA903U depends on the input sampling frequency, configured via I2C bits IB1[7-6]. Typical values are: 44.1 kHz - 465 μs, 48 kHz - 430 μs, 96 kHz - 50 μs, and 192 kHz - 30 μs.

I2C Bus Interface: The FDA903U communicates with a microprocessor via a 2-wire I2C bus interface (SDA and SCL lines). The I2C protocol includes a start condition, chip address byte, subaddress byte, data sequence, and a stop condition. The maximum clock speed is 400 kbit/sec. Addresses range from 1110000 to 1110111.

Writing Procedure: Two methods exist: without increment (I bit set to 0) and with increment (I bit set to 1). The former writes only to the addressed register, while the latter writes sequentially from the addressed register.

Reading Procedure: Involves sending the device address and receiving data from the slave. To read a specific register, a write action is needed to specify the register, followed by a read action.

Data Validity: Data on the SDA line must be stable during the high period of the clock. Changes occur only when the clock signal on the SCL line is low.

Start and Stop Conditions: A start condition is a high to low transition of the SDA line while SCL is high. A stop condition is a low to high transition of the SDA line while SCL is high.

Byte Format: Each byte transferred must contain 8 bits, followed by an acknowledge bit. The MSB is transferred first.

Acknowledge: The transmitter puts a resistive high level on the SDA line during the acknowledge clock pulse, while the receiver pulls it low.

I2C Timing: The I2C bus protocol and its timings are detailed, with parameters like SCL frequency (max 400 kHz), setup and hold times for start and stop conditions, and data line setup and hold times.

I2S, I2C, and Enable Relationship: The FDA903U requires the I2S clock for I2C programming. The I2C commands are ineffective without the I2S clock, though they remain stored in I2C registers.

I2C Registers: Various registers (IB0 to IB14) are detailed, each with specific data bits and default values for functions like digital input settings, frame sync frequency, power limiting, diagnostic configurations, and more.

Technical Document Summary

1. Specifications and Data Registers: This section provides detailed information on various data registers used in the FDA903U I2C interface. Each table describes the data bits, their types, and definitions for different functionalities such as offset presence, thermal warnings, diagnostic pulses, and current sensing. Key registers include:

DB0-ADDR: Manages offset and open load detection.
DB1-ADDR: Handles thermal warnings and overvoltage shutdown detection.
DB2-ADDR: Covers channel diagnostics including overcurrent and short load detection.
DB3-ADDR: Contains DC diagnostic error codes.
DB4-ADDR and DB5-ADDR: Provide current sensing data.
DB6-ADDR: Includes high voltage mute and thermal shutdown detection.

2. Package Information: The document outlines the package specifications for the FDA903U, specifically the PowerSSO-36 (slug-up) package. It includes mechanical data with dimensions and tolerances, as well as marking information. The package is designed to meet environmental requirements under the ECOPACK standards.

3. Revision History: The revision history section notes changes made to the document, including the removal of a watermark and modifications to electrical characteristics test conditions. The document has undergone two revisions since its initial release in January 2019.

4. Important Notice: The document concludes with a disclaimer from STMicroelectronics regarding the potential for changes to the document and products, the responsibility of purchasers, and the terms of use for ST products.

Catalog excerpts

FDA903U 1 x 45 W class D digital input automotive power amplifier with ILoad current monitoring, wide voltage operation range for car audio and telematic Datasheet - production data Description The FDA903U is a single bridge class D amplifier, designed in the most advanced BCD technology, intended for any automotive audio application (car radio, telematics and e-call, noise and tone generators, etc). AEC-Q100 qualified Integrated 108 dB D/A conversion I2S and TDM digital input (4/8/16CH TDM) Input sampling frequency: 44.1 kHz, 48 kHz, 96 kHz, 192 kHz Full I2C bus driving (3.3/1.8 V) CISPR 25 - Class V (Fourth edition) Very low quiescent current Output lowpass filter included in the feedback allowing outstanding audio performances Wide operating supply range from 3.3 to 18 V, suitable for car radio, telematics and e-call MOSFET power outputs allowing high output power capability – 1 x 25 W /4 Ω @ 14.4 V, 1 kHz THD = 1% – 1 x 30 W /4 Ω @ 14.4 V, 1 kHz THD = 10% 2 Ω loads driving Power limiting function (configurable through I2C) I2C bus diagnostics: – Short to VCC/GND – Short load and open load detection (also in play mode) – Four thermal warnings DC offset detector (also in play) and 'hot spot' detection Clipping detector Integrated thermal protection Legacy mode ('no I2C' mode), 4 configurable settings Short circuit and ESD integrated protections Package: PowerSSO-36 exposed pad up July 2019 This is information on a product in full production. The FDA903U integrates a high performance D/A converter together with powerful MOSFET outputs in class D, so it is very compact and powerful, moreover it reaches outstanding efficiency performances (90%). It has a very wide operating range: it can be operated both with standard car battery levels (5.5-18 V operating, compatible to load dump pulse) and with external step-down generated voltages or emergency battery (since it is compatible to minimum 3.3 V operative). The feedback loop includes the output L-C lowpass filter, allowing superior frequency response linearity and lower distortion. FDA903U is configurable through I2C bus interface and integrates a complete diagnostics array specially intended for automotive applications including innovative open load and DC offset detection in play mode. Thanks to the solutions implemented to solve the EMI problems, the device is intended to be used in the standard single DIN car-radio box together with the tuner. Moreover FDA903U features a configurable power limiting function, and can be optionally operated under no I2C mode ('legacy mode'). Table 1. Device summary Order code Tape & reel

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Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical curves of the main electrical parameters . . . . . . . . . . . . . . . . . . . 15 LC filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Load possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 6.2 Diagnostic Vcc-Gnd state . . . . . . . . . . . . . . . . . . . . . . . . . . ....

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Relation with short circuit protection activation . . . . . . . . . . . . . . . . . . . 36 Diagnostic time-line diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Open load in play detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.4.1 Open load in play detector operation overview . . . . . . . . . . . . . . . . . . . 40 Processing bandwidth range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Audio signal evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Input offset detector...

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Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Instruction bytes- “I00xxxxx” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Data bytes - “I01xxxxx” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PowerSSO-36 (slug-up) package information . . . . . . . . . . . . . . . . . . . . . 76 PowerSSO-36 (slug up) marking information . . . . . . . . . . . . . . . . . . . . . . 78

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List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36.

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List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . ....

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Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Load range detection configured properly setting IB5 d7-d6 . . . . . . . . . . . . . . . . . . . . . . . 36 DC diagnostic before turn on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Short to VCC at device turn on . ....

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