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FDA803D

Product catalog summary

Overview: The FDA803D is a 45 W class D digital input automotive power amplifier designed for car audio and telematics applications. It features a wide voltage operation range and integrated diagnostics.

Key Features:

AEC-Q100 qualified for automotive applications.
Integrated 108 dB D/A conversion with I2S and TDM digital input support.
Supports input sampling frequencies of 44.1 kHz, 48 kHz, 96 kHz, and 192 kHz.
Operates on a wide supply range from 3.3 to 18 V.
Includes MOSFET power outputs for high output power capability.
Power limiting function configurable via I2C.
Comprehensive diagnostics including short to VCC/GND, load detection, and thermal warnings.
Integrated thermal protection and ESD protection.

Specifications:

Output power: 1 x 25 W /4 Ω @ 14.4 V, 1 kHz THD = 1% and 1 x 30 W /4 Ω @ 14.4 V, 1 kHz THD = 10%.
Supports 2 Ω load driving.
Package: PowerSSO-36 with exposed pad down.

Diagnostics and Protection:

I2C bus diagnostics for short circuits, open load detection, and thermal warnings.
DC offset and 'hot spot' detection.
Clipping detector and integrated thermal protection.

Additional Features:

Legacy mode with four configurable settings.
Hardware mute pin and power limiter function.
AM operation mode and noise gating.

Interface and Control:

Full I2C bus driving capability with 3.3/1.8 V support.
I2S bus interface with standard and TDM modes.
Detailed I2C register and timing information provided.

Description: The FDA803D is a single bridge class D amplifier designed using advanced BCD technology for automotive audio applications such as car radios, telematics, and noise generators. It integrates a high-performance D/A converter with powerful MOSFET outputs, achieving up to 90% efficiency. The device operates over a wide voltage range (3.3V to 18V) and includes a feedback loop with an output L-C low-pass filter for superior frequency response and lower distortion. It is configurable via an I2C bus interface and includes diagnostics for automotive applications, such as open load and DC offset detection.

Block Diagram: The document includes a block diagram illustrating the internal structure and connections of the FDA803D, highlighting its integration of digital and analog components.

Pins Description: The FDA803D features a detailed pin configuration, including power supply, ground connections, I2C and I2S interfaces, and various enable and diagnostic pins. Key pins include the I2C data and clock pins, I2S data and clock inputs, and hardware mute pin.

Application Diagram: An application diagram is provided to demonstrate typical usage scenarios and connections for the FDA803D in automotive audio systems.

Electrical Specifications: The document outlines the absolute maximum ratings, thermal data, and electrical characteristics of the FDA803D. Key parameters include supply voltage range, quiescent current, output power, total harmonic distortion (THD), and power supply rejection ratio (PSRR). The device supports a wide range of operating conditions and includes features like overcurrent protection and thermal shutdown.

Audio Performance: The FDA803D delivers significant output power with low THD, offering high dynamic range and signal-to-noise ratio. It supports various gain settings and includes a mute function with specific voltage thresholds.

I2C and I2S Interfaces: The device supports I2C and I2S interfaces for configuration and data transmission, with specified voltage levels and clock frequencies. The I2C interface allows for flexible device control and diagnostics.

Control Pins Characteristics: The document specifies the voltage levels for enable pins, with low voltage at 0.9 V and high voltage at 2.4 V. These parameters are crucial for the proper functioning of the control pins.

Clipping and Offset Detector: The clipping detector has a threshold distortion (THD) at 100 Hz with an average Vclipdet of 2 V, ranging from 5% to 9%. The clipping saturation voltage is between 150 mV and 300 mV, and the leakage current at the CD pin is up to 15 μA. The input and output DC offset detection thresholds are also specified.

Electrical Specifications: The document provides detailed electrical characteristics, including efficiency and power dissipation across various conditions and configurations. Figures illustrate these parameters under different supply voltages and load resistances.

LC Filter Design: The performance of a Class D amplifier is significantly influenced by the LC filter design. The document discusses the importance of component selection for size, cost, EMI suppression, and efficiency. It highlights the challenges of non-linear behavior in inductors and capacitors and the impact on Total Harmonic Distortion (THD).

Load Possibilities: The FDA803D supports various load configurations, including 2 Ω and 4 Ω loads, with specific voltage limits for each configuration.

Finite State Machine: The FDA803D features a finite state machine that manages amplifier functionality. It allows for different I2C address selections and legacy modes. The document outlines the states such as Standby, Diagnostic Vcc-Gnd, ECO-mode, MUTE-PLAY, and diagnostic states, detailing the conditions and transitions between these states.

Muting Function Architecture: The muting function uses a mixed signal approach, activated by various mute command signals such as high voltage, low battery, hardware, thermal, and I2C mute. The document describes the operation of Analog-Mute and Digital-Mute actuators and their advantages in providing robust muting functionality.

Figures and Tables: The document includes numerous figures and tables illustrating efficiency, power dissipation, output power, THD, frequency response, and muting function architecture. These visual aids provide a comprehensive understanding of the amplifier's performance under different conditions.

Hardware Mute Pin: The FDA803D features a hardware mute pin (HWMute) that mutes the device when low and plays when high. A pull-up current generator ensures the device plays if the pin is floating. An external pull-down open drain is required for hardware mute, with RMute less than 60 kΩ.

Power Limiter Function: This function protects small speakers by limiting the maximum power delivered to the load. Configurable via I2C, it operates independently of supply voltage and applies different gains based on signal amplitude and desired attenuation. The power limiter can be controlled through I2C settings and is only configurable in the MUTE state.

Diagnostic Features: The FDA803D includes diagnostic functions to detect faults such as short circuits, open loads, under/over voltage, and more. Faults are stored in the I2C interface and can trigger interrupts. The DC diagnostic routine checks load connection status and is immune to false detections from voltage variations or mechanical stress. Short to Vcc/GND diagnostics detect hard and soft shorts, with results communicated via I2C.

Open Load in Play Detector: This feature detects speaker detachment during PLAY state by evaluating audio signal characteristics and measuring differential current. It processes audio bandwidth up to 2kHz and requires accurate current measurement. The test results are communicated via I2C, and the feature includes configurable impedance thresholds.

Input and Output Offset Detectors: The input offset detector identifies offsets from the audio signal source, setting a flag if the offset exceeds a threshold. The output voltage offset detector identifies voltage offsets on the output, setting a flag if the condition persists for 90ms. Both features provide robust detection and are active in MUTE and PLAY states.

Output Current Offset Detector:

Operation Principle: Detects differential DC current offset between output pins OUTP and OUTM. The offset is calculated as IOFFSET = |IOUTP-IOUTM|/2 and compared to a threshold set via I2C bits IB10[4,3].
Result Communication: Controlled via I2C. Detection starts by setting IB3[3]='1'. Results are communicated by setting DB0[6] and DB0[5] flags.
Hot Spot Detection: Detects soft shorts to Vcc or Gnd, enhancing robustness against hot spots.

PWM Pulse Skipping Detector:

Function: Detects PWM stage saturation by identifying skipped PWM commutations. Enabled by setting IB5[5,4]='01'.
Output: Provides output via CDDiag pin and sets flag DB1[0]='1'.

Thermal Protection:

Levels: Three levels of protection against over-temperature: communication of temperature thresholds, output signal attenuation, and power stage shutdown.
Thresholds: Temperature thresholds can be reduced by 15°C by setting I2C bit IB12[7].

Watch-dog:

Function: Enabled by setting I2C IB9[4]='1'. Resets timer at each Word Select line rising edge. Sends muting command and sets flag DB6[2] upon timeout.

Error Frame Check:

Function: Permanently enabled. Checks coherence of rising edges on Clock line with I2C configuration. Sets flag DB6[1] if an error is detected.

Additional Features:

AM Operation Mode: Allows selection of PWM switching frequency to avoid EM interference. Includes Low Radiation Function (LRF) to minimize PWM duty cycle.
Noise Gating: Reduces noise when output signal is at non-audible levels. Enabled by default.
Dither PWM: Improves EMC performance by modulating PWM period. Suggested for use with In Phase modulation.

I2S Bus Interface:

Components: Composed of Clock line, Word Select line, and Serial Data line. Supports various sampling frequencies and data formats.
Timing Requirements: Detailed timing requirements for I2S interface provided.

I2C Bus Interface:

Protocol: Data transmission via SDA and SCL lines. Supports multiple addresses and includes start/stop conditions.
Writing/Reading Procedures: Describes procedures for writing and reading data, including auto-increment options.

Data Validity: The data on the SDA line must remain stable during the high period of the clock. Changes in data line states are only permissible when the SCL line is low.

Start and Stop Conditions: A start condition is indicated by a high to low transition on the SDA line while SCL is high. Conversely, a stop condition is a low to high transition on the SDA line while SCL is high.

Byte Format: Each byte transferred must contain 8 bits, followed by an acknowledge bit, with the MSB transferred first.

Acknowledge: During the acknowledge clock pulse, the transmitter sets a resistive high level on the SDA line, while the receiver must pull it down to low.

I2C Timing: The document provides detailed timing parameters for the I2C bus protocol, including SCL frequency, period, and setup/hold times for start and stop conditions.

I2S, I2C, and Enable Relationship: The FDA803D supports both I2C and I2S communication. The I2C interface requires the presence of the I2S clock, and commands are not effective without it. The digital machine enters standby if the I2S clock is lost.

I2C Register Instructions: The document details various instruction bytes (IB0 to IB14) and their configurations, including digital input settings, frame sync frequencies, power limiting configurations, and diagnostic settings.

Data Bytes: Data bytes (DB0 to DB6) are described, indicating types and definitions for various diagnostic flags and error codes.

Package Information: The FDA803D is available in ECOPACK® packages, with detailed mechanical data provided for the PowerSSO-36 package.

Specifications: The document provides detailed specifications for the PowerSSO-36 package, including dimensions D and E1, which do not account for mold flash or protrusions. The allowable mold flash is 0.25 mm per side for D and 0.15 mm per side for E1. These dimensions represent the maximum plastic body size, including mold mismatch.

Package Information: The FDA803D package includes marking information for both engineering and commercial samples. Engineering samples are marked with 'ES' and are intended for electrical compatibility evaluation only, with usage restrictions unless authorized by ST. Commercial samples are fully qualified with no usage restrictions.

Revision History: The document includes a revision history table, noting the initial release on 19-Feb-2018 and a change in confidentiality level to public on 03-May-2018.

Important Notice: STMicroelectronics reserves the right to make changes to products and documents without notice. Purchasers are responsible for obtaining the latest information and assume liability for the use of ST products. No intellectual property rights are granted, and resale with different provisions voids warranties.

Catalog excerpts

FDA803D 1 x 45 W class D digital input automotive power amplifier with diagnostics, wide voltage operation range for car audio and telematic Datasheet - production data  2 Ω loads driving  Power limiting function (configurable through I2C)  I2C bus diagnostics: – Short to VCC/GND – Short load and open load detection (also in play mode) – Four thermal warnings  DC offset detector (also in play) and 'hot spot' detection  Integrated thermal protection  Legacy mode ('no I2C' mode), 4 configurable settings  I2S and TDM digital input (4/8/16CH TDM)  Input sampling frequency: 44.1 kHz, 48 kHz, 96 kHz, 192 kHz  Full  Short circuit and ESD integrated protections  Package: PowerSSO-36 exposed pad down Table 1. Device summary  CISPR 25 - Class V (Fourth edition) Order code  Very low quiescent current  Output lowpass filter included in the feedback allowing outstanding audio performances Tape & reel  Wide operating supply range from 3.3 to 18 V, suitable for car radio, telematics and e-call  MOSFET power outputs allowing high output power capability – 1 x 25 W /4 Ω @ 14.4 V, 1 kHz THD = 1% – 1 x 30 W /4 Ω @ 14.4 V, 1 kHz THD = 10% May 2018 This is information on a product in full

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Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Typical curves of the main electrical parameters . . . . . . . . . . . . . . . . . . . 17 LC filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Load possibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Finite state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 7.2 Diagnostic Vcc-Gnd state . . . . . . . . . . . . . . . . . . . . . . . . . . ....

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Power limiter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Relation with short circuit protection activation . . . . . . . . . . . . . . . . . . . 37 Diagnostic time-line diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Open load in play detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11.4.1 Open load in play detector operation overview . . . . . . . . . . . . . . . . . . . 41 Processing bandwidth range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Audio signal...

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Timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Group delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Instruction bytes- “I00xxxxx” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Data bytes - “I01xxxxx” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PowerSSO-36 (exposed pad) package information . . . . . . . . . . . . . ....

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List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34.

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List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . ....

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Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. DC Diagnostic in Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Short circuit protection activation - Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Short Circuit Protection activation due to short across load, short...

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Description The FDA803D is a single bridge class D amplifier, designed in the most advanced BCD technology, intended for any automotive audio application (car radio, telematics and e-call, noise and tone generators, etc). The FDA803D integrates a high performance D/A converter together with powerful MOSFET outputs in class D, so it is very compact and powerful, moreover reaches outstanding efficiency performances (90%). It has a very wide operating range: it can be operated both with standard car battery levels (5.5-18 V operating, compatible to load dump pulse) and with external step-down generated...

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Block diagram Block diagram Figure 1. Block diagram

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Pins description Pins description Figure 2. Pins connection diagram Table 2. Pins list function Pin # 1 Channel half bridge minus, Power Ground Channel half bridge minus, Power Supply Channel half bridge minus, Output Channel half bridge minus, Output Digital ground Digital supply Device slug connection Channel half bridge minus, Feedback Not connected Clipping detector and diagnostic output pin

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Pins description Table 2. Pins list function Pin # Positive digital supply V(SVR)+0.9V (Internally generated) Negative digital supply V(SVR)-0.9V (Internally generated) test pin, left open I2S/TDM Sync input /Word Select input Analog ground Analog supply Positive Analog Supply V(SVR)+2.5V (Internally generated) Negative Analog Supply V(SVR)-2.5V (Internally generated) Channel half bridge plus, Output Channel half bridge plus, Output Channel half bridge plus, Power Supply Channel half bridge plus, Power Ground Supply Voltage Ripple Rejection Capacitor Hardware mute pin Channel half bridge plus,...

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FDA803D

FDA803D

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