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SR250Gated Integrator

SR250Gated Integrator
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Gated Integrators and Boxcar Averagers SR250 — Gated integrator with gate width to 2 ns · Gate width from 2 ns to 15 µs (expandable to 150 µs) · Internal rate generator · Active baseline subtraction · Shot-by-shot output · Gate output for precise gate timing · Average 1 to 10,000 samples · DC to 20 kHz repetition rate · Low jitter (<20 ps + 0.01 % of delay) SR250 Gated Integrator The SR250 Gated Integrator is a versatile, high-speed NIM module designed to recover fast analog signals from noisy backgrounds. the signal, and makes the instrument a particularly useful component in a computer data acquisition system. Triggering The SR250 consists of a gate generator, a fast gated integrator, and exponential averaging circuitry. The gate generator, triggered internally or externally, provides an adjustable delay from a few nanoseconds to 100 ms before it generates a continuously adjustable gate with a width between 2 ns and 15 µs. The gate delay can be set from the front panel or automatically scanned by applying a rear-panel control voltage. Scanning the gate allows the recovery of entire waveforms. The SR250 may be triggered internally or externally. The internal rate generator is continuously variable from 0.5 Hz to 20 kHz in nine ranges. The external trigger pulse may be as short as 5 ns, allowing the unit to be triggered with fast pulses from photodiodes and photomultipliers. Single shot and line triggering can also be selected. Signal Inputs The fast gated integrator integrates the input signal during the gate. The output from the integrator is then normalized by the gate width to provide a voltage proportional to the average of the input signal during the sampling gate. This signal is further amplified and sampled by a low-droop sample-andhold amplifier, and output via a front-panel BNC connector. The last sample output provides a shot-by-shot analysis of Stanford Research Systems The sensitivity (Vin/Vout) of the instrument may be set from 1 V/V to 5 mV/V. If additional gain is required, the SR250 can be used with the SR240A preamplifier. The input is protected to 100 V and has a 1 MΩ input impedance. An input filter rejects unwanted signals before the input is sampled by the integrator. Unwanted DC input offsets are easily nulled with a 10-turn potentiometer.

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Gate Timing The delay of the sample gate from the trigger is set by the delay multiplier and scale. The delay scale is multiplied by the setting on the 10-turn multiplier dial, allowing continuously adjustable delays from a few nanoseconds to 100 ms. The delay multiplier may also be changed from the rear-panel control voltage input—a useful feature in applications requiring a scanning gate. Zero to ten volts at this input overrides the front-panel 0 to 10x delay multiplier. Insertion delay from trigger to gate is only 25 ns, and gate-delay jitter is only 20 ps + 0.01 % of the full-scale...

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Droop rate Average polarity and baseline subtraction Toggle output Reset button Remote reset Trigger Internal trigger Line trigger External trigger Manual trigger Trigger LED 0.5 Hz to 20 kHz The gate generator may be triggered from AC line with adjustable phase. 1 MΩ input impedance. Trigger threshold adjustable from 0.5 to 2 V. Input protected to ±100 VDC. Trigger pulse must be over threshold for >5 ns with a rise time <1 µs. The unit will trigger if trigger threshold is scanned through 0 VDC. LED blinks with each trigger. Delay Delay scale 1 ns to 10 ms Delay multiplier 0 to 10× using...

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