intelligent Panel Controller for Standard Frame Rate System The CXD4728R is an image signal processor for Fiat Panel Display system, which can improve a quality of color representation, contrast feeling, and resolution feeling. This LSI has some unique features; the function "Bi-axial Color Control" that improves a quality of color representation by changing colors on x-y chromaticity graph. The method of color adjustment is easier and the operability is improved compared to the general Hue adjustment. The function "intelligent Contrast Synthesizer" improves the contrast feelings and resolution feeling. Especially a contrast for the dark scene is improved. This function is realized only by signal processing, and it does not depend on back-light system. The function "Two Dimensions Sharpness" improves sharpness and spacial effect. And two sets of 12-bit RGB independent gamma compensation can change the gamma curve and white balance. Those functions can adjust a picture depending on user's liking or characteristics of various panels. The connection to a customer system is easy and also the picture adjustment is easy by small registers. It is not needed to largely reconstruct existing system software. (Applications: Color TFT-LCD TV, Panel Module) ♦ Bi-axial Color Control Function ♦ intelligent Contrast Synthesizer Function ♦ Brightness, Color, Contrast Control ♦ Double Gamma Correction with full-size 12-bit RGB independent LUT ♦ Dither function for 8-bit panel system ♦ LVDS Receiver and Transmitter which support single/dual links 8-bit Rigor 10-bit RGB ♦ Input/Output frequency range 65MHz to 85MHz (SS included) ♦ Tolerates Spread Spectrum Clock at the LVDS input ♦ SSCG (spread spectrum clock generator) for LVDS Tx clock ♦ Support display resolutions WXGA (1366 x 768p) or Full-HD (1920 x 1080p) ♦ Support l2C Slave Interface for external host CPU (100kHz to 400kHz) ♦ Support l2C Master Interface for stand-alone startup with max. 128K-bit external EEPROM (optional). ♦ No need external DRAM Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD4728R Package LQFP 128 pins (0.5mm pin pitch, body size 20mm 14mm) 1. Block Diagram intelligent Image Processor RXBCK (Clock) PLL B DE Clock Clock R G B DE Register Interface Block I2C Slave Interface I2C Master Interface Clock Circuits I2C Bus Through Path SCL/SDA 2 bits Slave Address Selector Host I/F SCL/SDA Master Address Selector Master Busy Signal Clock Input Reset Input 20MHz to 30MHz (25MHz for I2C Master I/F use) EEPROM for start-up (Optional) Fig.1-1. intelligent Panel Controller Block Diagram -2- TXA0 to TXA4 (8 bits/10 bits) 5ch LVDS Tx SSCG PLL 5ch LVDS Tx G DE Dither 5ch LVDS...

CXD4728R 3. Pin Description Pin No. Pin name Type Pin descriptions Condition at hard reset Note 4 RXA0N LVDS IN LVDS receiver data input, Link A, Channel 0 (–) (*1) 5 RXA0P LVDS IN LVDS receiver data input, Link A, Channel 0 (+) (*1) 6 RXA1N LVDS IN LVDS receiver data input, Link A, Channel 1 (–) (*1) 7 RXA1P LVDS IN LVDS receiver data input, Link A, Channel 1 (+) (*1) 8 RXA2N LVDS IN LVDS receiver data input, Link A, Channel 2 (–) (*1) 9 RXA2P LVDS IN LVDS receiver data input, Link A, Channel 2 (+) (*1) 10 RXACKN LVDS IN LVDS receiver clock input for Link A (–) (*1) 11 RXACKP LVDS IN LVDS receiver...

CXD4728R Pin No. Pin name Type Pin descriptions Condition at hard reset Note 95 TXACKP LVDS OUT LVDS transmitter clock output for Link A (+) Uncertain value (High or Low) (*2) 90 TXA3N LVDS OUT LVDS transmitter data output, Link A, Channel 3 (–) Uncertain value (High or Low) (*2) 89 TXA3P LVDS OUT LVDS transmitter data output, Link A, Channel 3 (+) Uncertain value (High or Low) (*2) 88 TXA4N LVDS OUT LVDS transmitter data output, Link A, Channel 4 (–) In 8-bit output mode, this pin is disabled. Uncertain value (High or Low) (*2) 87 TXA4P LVDS OUT LVDS transmitter data output, Link A, Channel...

CXD4728R Pin No. Pin name 107 IIC_MST_EN 3.3V IN I2C master interface enable. High: Enable, Low: Disable 112 TESTMODE 3.3V IN Always Connect this pin to digital ground (VSSIO). This pin is used only for Sony internal test. Type Pin descriptions 114 117 118 119 120 N.C Do not connect. 121 126 127 17 35 16 34 2 20 3 21 RXAVDD 3.3V power RXAVSS GND RXDVDD 1.2V power RXDVSS GND Analog power supply (3.3V) for LVDS receiver Ground for LVDS receiver Digital power (1.2V) for LVDS receiver Ground for LVDS receiver 72 81 TXAVDD33 3.3V power Analog power supply (3.3V) for LVDS transmitter 83 TXPLLAVDD 1.2V...

CXD4728R Pin No. Pin name Type Pin descriptions Condition at hard reset Note 18 40 47 60 VDD 1.2V power VSS GND Digital supply voltage (1.2V) for core circuit 110 124 128 1 19 36 48 Ground for core circuit 61 111 125 39 41 45 57 62 VDDIO 3.3V power VSSIO GND Ground for I/O Exposed Pad GND Ground for LVDS transmitter Digital supply voltage (3.3V) for I/O 105 108 116 123 37 42 46 58 63 106 109 115 122 — *1 *2 *3 *4 *5 *6 (*6) Unused pins must be fixed to High (3.3V) or OPEN for LVDS Rx. Unused pins must be OPEN for LVDS Tx. Active Low reset is required after turn On. The external pull-up registers...

CXD4728R 4. Electrical Characteristics 4-1. Absolute Maximum Ratings Item Symbol Min. Max. Unit 3.3V digital I/O –0.5 +4.6 V LVDS Rx, Tx I/O RXAVDD, TXAVDD33, TXDVDD33 –0.5 +4.6 V Core logic VDD –0.5 +1.6 V LVDS Rx, Tx logic RXDVDD, TXDVDD –0.5 +1.6 V PLL Power supply voltage VDDIO PLLVDDA, TXPLLAVDD, TXPLLDVDD –0.5 +1.6 V Tj –40 +125 C Min. Typ. Max. Unit Operating junction temperature 4-2. Recommended Operating Conditions Item Symbol 3.3V digital I/O 3.0 3.3 3.6 V LVDS Rx, Tx I/O RXAVDD, TXAVDD33, TXDVDD33 3.0 3.3 3.6 V Core logic VDD 1.1 1.2 1.3 V LVDS Rx, Tx logic RXDVDD, TXDVDD 1.1 1.2 1.3...