Ultra low power Audio Decoder LSI The CXD5091AGG is an audio decoder LSI that achieves super-low power consumption and supports many codecs. Useful interface such as NAND/NOR flash memory and Memory Stick is supported, and it comprises analog circuits such as audio D/A converter and SAR A/D converter. The CXD5091 AGG is suitable for portable audio players and cellular phone audio backend. NAND flash interface Serial interface Clocked serial interface Memory Stick interface Audio interface Watchdog timer SRAM, NOR flash slave compatible Host processor can be connected. An external acknowledge device is also supported. 4-symbol ECC, Reed-Solomon error correction X 2ch (1ch supports up to 3Mbps baud rate.) Either analog audio interface or l2S bus interface can be selected as transfer PHY included, Low/Full/High-speed device, 5 end points, Control/Interrupt/ Bulk/Isochronous transfer X 8ch, internal clock/external event trigger Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Sampling rate converter ♦ Signal processing accelerator: Virtual Mobile Engine 8 to 96kHz sampling frequency is converted to 44.1 kHz. Peak detection 116 (When all multiplexed pins are setas GPIO), Direction individually selected 45.1584MHz input, Crystal/Ceramic selectable 12MHz input, Crystal/Ceramic selectable In this data sheet abbreviations shown below are used to simplify descriptions.

CXD5091AGG Pin Description Table 2 shows the pin description. Table 2. Pin Description Pin name Direction Description NAD0/GPIOC0 I/O / I/O NAD1/GPIOC1 I/O / I/O NAD2/GPIOC2 I/O / I/O NAD3/GPIOC3 I/O / I/O NAD4/GPIOC4 I/O / I/O NAD5/GPIOC5 I/O / I/O NAD6/GPIOC6 I/O / I/O NAD7/GPIOC7 I/O / I/O NCLE/GPIOC8 Output / I/O Command latch enable NALE/GPIOC9 Output / I/O Address latch enable NCE0/GPIOC10 Output / I/O NAND chip enable bank 0 NCE1/GPIOC11 Output / I/O NAND chip enable bank 1 NCE2/GPIOC12 Output / I/O NAND chip enable bank 2 NCE3/GPIOC13 Output / I/O NAND chip enable bank 3 NRE/GPIOC14 Output...

Power Supply/GND Pins Table 3 shows the correspondence of power supply/GND pins to general pins. Table 3. Power Supply/GND Correspondence to General Pins VREFL, AOUTL, AOUTR, VREFR

Table 4 shows the state of pins at certain conditions. Table 4. State of Pins

n For Dlom, DI0L1, DI0H2 and DI0L2, refer to Table 7 Electrical Characteristics.

The I/O types in Table 4 are illustrated below. Output data Output enable Input data Output data Output enable Input data- Note 2. I/O (Schmitt Input) Input data Input data-<OÎL Output data Note 4. Input (Schmitt Input) Input data-"CXi. Note 7. I/O (5V Tolerant, Schmitt Input)

Electrical Characteristics and Operating Conditions 1. Absolute Maximum Ratings Table 5. Absolute Maximum Ratings

2. Recommended Operating Conditions Table 6. Recommended Operating Conditions n Refer to I/O Type column in Table 4 State of Pins. *2 Offset for DVDKO-2 shall be less than 0.3V. *3 When SCL/GPIOKO and SDA/GPIOK1 are in use, the minimum voltage must be as low as 1.8V.

3. Electrical Characteristics Under Recommended Operating Temperature Range Table 7. Electrical Characteristics

n Refer to GPIO setting in user's manual. *2 Refer to Output Drivability column in Table 4 State of Pins. *3 Refer to Output Drivability column in Table 4 State of Pins. *4 Ceramic mode: For OSC45, keep MCSEL pin "H". For OSC12, set SCSEL bit to "1 " in SCLE register *5 Crystal mode: For OSC45, keep MCSEL pin "L". For OSC12, set SCSEL bit to "0" in SCLE register *6 Set SPLLEN bit to "1 ", set SFDEV1 bit to "0", and set SFDEV0 bit to "1 " in SCLE register (3000001 Oh). *7 Set SOSC bit to "1 " in CLC register (30000000h) and set SPLLEN bit to "0" in SCLE register (3000001 Oh), then set to stop...

Analog Block 3. Crystal/Ceramic and Oscillator Connection Exact matching parameters for feedback resistance and capacitance depend on the system. (a) Crystal/Ceramic (b) External clock

Recommended Power-on/Power-off Sequence DVDKO-2 and analog power supply should be powered on prior to DVDIOO-2 power supply. The system must wait until its stabilization by asserting RST for over 1 ms. There is not any requirement for supply order between DVDKO-2 and analog power supply. The power-off sequence does not care the state of RST. Analog power supply Analog power supply

Package Outline PACKAGE STRUCTURE Sony Corporation