32Mb LW R-R HSTL High Speed Synchronous SRAM (1Mb x 36) The CXK77K36R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 1,048,576 wordsby 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, pro- viding a high-performance user interface. All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the Kdifferential input clock. During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.Sleep (power down) capability is provided via the ZZ input signal. Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an externalcontrol resistor RQ between ZQ and V > SS , the impedance of the output drivers can be precisely controlled.333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset ofIEEE standard 1149.1 protocol. > 3 Speed Bins Cycle Time / Access Time -3 3.0ns / 1.6ns-33 3.3ns / 1.6ns-4 4.0ns / 2.0ns?Single 2.5V power supply (V > DD ): 2.5V ձ 5% Note : 1.8V V > DD is also supported. Please contact Sony Memory Marketing Department for further information.?Dedicated output supply voltage (V > DDQ ): 1.5V 0.1V Note : 1.8V V > DDQ is also supported. Please contact Sony Memory Marketing Department for further information.?HSTL-compatible I/O interface with dedicated input reference voltage (V > REF ): 0.75V typical?Register - Register (R-R) read protocol?Late Write (LW) write protocol?Full read/write coherency ?Byte Write capability?Differential input clocks (K/K )?Asynchronous output enable (G )?Sleep (power down) mode via dedicated mode pin (ZZ)?Programmable output driver impedance?JTAG boundary scan (subset of IEEE standard 1149.1) ?119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package > 32Mb LW R-R, rev 0.61 / 22March 16, 2004 size="-1">

DDQ SASANCSASAV > DDQ BNCSASASA(32M)SASANCCNCSASAV > DD SASANCDDQcDQcV > SS ZQV > SS DQbDQbEDQcDQcV > SS SS V > SS DQbDQbFV > DDQ DQcV > SS G V > SS DQbV > DDQ GDQcDQcSBW cNCSBW bDQbDQbHDQcDQcV > SS NCV > SS DQbDQbJV > DDQ V > DD V > REF V > DD V > REF V > DD V > DDQ KDQdDQdV > SS KV > SS DQaDQaLDQdDQdSBW dK SBW aDQaDQaMV > DDQ DQdV > SS SW V > SS DQaV > DDQ NDQdDQdV > SS SAV > SS DQaDQaPDQdDQdV > SS SAV > SS DQaDQaRNCSAM1 > (1) V > (2) DD M2 SANCTNCNC(x18)SASA(x36)SANC(x18)ZZUV > (3) DDQ TMSTDITCKTDORSVD V > DDQ Notes :1. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it...

x(t (t OperationDQ(t > n )SW (t > n )SBW > n )G > n )DQ(t > n+1 )X1XXXXSleep (Power Down) ModeHi - ZHi - Z ↑ 01XXXDeselect***Hi - Z ↑ 001X1ReadHi - ZHi - Z ↑ 001X0Read***Q(t > n ) ↑ 0000XWrite All Bytes***D(t > n ) ↑ 000XXWrite Bytes With SBW x = 0***D(t > n ) ↑ 0001XAbort Write***Hi - Z Notes: 1.1Ӕ = input highӔ; 0Ӕ = input lowӔ; XӔ = input donӒt care.2. ԓ*** indicates that the input requirement or output state is determined by the previous operation.3.DQs are tri-stated in response to Write and Deselect commands, one cycle after the command is sampled. > Sleep (power down) mode is provided...

(V > o DD = 2.5V α 5%, V > SS = 0V, T > A = 0 to 85 C) > LI V > IN = V > SS to V > DDQ -5---5uAInput Leakage Current (M1, M2)I > MLI V > MIN = V > SS to V > DD -5---5uAOutput Leakage CurrentI V > OUT = V > SS to V > DDQ LO -5---5uAAverage Power Supply Operating CurrentI G = V > IH DD-3 I = 0 mASS ------ --------- ---650600 540mAPower SupplyStandby CurrentI I > OUT DD-33 I > DD-4 = V > IL , ZZ = V > IL I > OUT = 0 mAZZ = V > SB ------180mA1Output High VoltageV > IH I > OH = -6.0 mARQ = 250 > OH V - 0.4------VOutput Low VoltageV Ω > DDQ I > OL = 6.0 mARQ = 250 > OL ------0.4VOutput Driver ImpedanceR...

ItemSymbolConditionsUnitsNotesInput Reference VoltageV > REF 0.75VInput High LevelV > IH 1.25VInput Low LevelV > IL 0.25VInput Rise & Fall Time2.0V/nsInput Reference Level0.75V Clock Input High VoltageV > KIH 1.25VV > DIF = 1.0VClock Input Low VoltageV > KIL 0.25VV > DIF = 1.0VClock Input Common Mode VoltageV > CM 0.75VClock Input Rise & Fall Time2.0V/nsClock Input Reference LevelK/K crossVOutput Reference Level0.75VOutput Load ConditionsRQ = 250 Ω See Figure 1below >

DummyDummy ReadReadReadReadReadWriteWriteWriteReadRead Read > t > KHKH t > KHKL t > KLKH t > AVKH t > KHAX IL t > WVKH t > KHWX t > WVKH t > KHWX t > GLQV t > GHQZ t > GLQX t > KHQV t > KHQX t > KHQZ t > DVKH t > KHDX t > KHQX1

t > THTL t > TLTH t > THTH t > MVTH t > THMX t > DVTH t > THDX t > TLQV t > TLQX

Bypass Register (DR - 1 Bit) The Bypass Register is one bit wide, and provides the minimum length serial path between TDI and TDO. It is loaded witha logic Γ0 when the BYPASS instruction has been loaded in the Instruction Register and the TAP Controller is in the ԓCap- ture-DR state. It is inserted between TDI and TDO when the BYPASS instruction has been loaded into the Instruction Reg-ister and the TAP Controller is in the ԓShift-DR state. ID Register (DR - 32 Bits) The ID Register is loaded with a predetermined device- and manufacturer-specific identification code when the IDCODEinstruction...

PACKAGE MATERIALBORAD TREATMENTLEAD MATERIALPACKAGE MASSSOLDER SONY CODEEIAJ CODEJEDEC CODE BGA-119P-021BGA119-P-1422EPOXY RESIN COPPER-CLAD LAMINATE1.1g This product utilizes lead (Pb) as one of the elements composing the package solder ball. The quantity of lead (Pb) per package isapproxmiately 70.81mg (1.7mg per ball * 119 balls * 35%). Lead (Pb) has been shown to be hazardous to the environment, and therefore may be subject to regulations within each country. > 32Mb LW R-R, rev 0.620 / 22March 16, 2004 size="-1">