32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18) The CXK77K18R320GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 2,097,152 wordsby 18 bits. This synchronous SRAMs integrates input registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R) read operations and Late Write (LW) write operations are supported, pro-viding a high-performance user interface. All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the Kdifferential input clock. During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.Sleep (power down) capability is provided via the ZZ input signal. Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an externalcontrol resistor RQ between ZQ and V > SS , the impedance of the output drivers can be precisely controlled.333 MHz operation is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using a subset ofIEEE standard 1149.1 protocol. > 3 Speed Bins Cycle Time / Access Time -3 3.0ns / 1.6ns-33 3.3ns / 1.6ns -4 4.0ns / 2.0ns?Single 1.8V power supply (V > DD ): 1.8V ձ 0.1V Note : 2.5V V > DD is also supported. Please contact Sony Memory Marketing Department for further information.?Dedicated output supply voltage (V > DDQ ): 1.5V to 1.8V typical?HSTL-compatible I/O interface with dedicated input reference voltage (V > REF ): V > DDQ /2 typical?Register - Register (R-R) read protocol?Late Write (LW) write protocol?Full read/write coherency ?Byte Write capability?Differential input clocks (K/K )?Asynchronous output enable (G )?Sleep (power down) mode via dedicated mode pin (ZZ)?Programmable output driver impedance?JTAG boundary scan (subset of IEEE standard 1149.1) ?119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package > 32Mb LW R-R, rev 0.81 / 23December 8, 2004 size="-1">

DDQ SASANCSASAV > DDQ BNCSASASA(32M)SASANCCNCSASAV > DD SASANCDDQbNCV > SS ZQV > SS DQaNCENCDQbV > SS SS V > SS NCDQaFV > DDQ NCV > SS G V > SS DQaV > DDQ GNCDQbSBW bNCV > SS NCDQaHDQbNCV > SS NCV > SS DQaNCJV > DDQ V > DD V > REF V > DD V > REF V > DD V > DDQ KNCDQbV > SS KV > SS NCDQaLDQbNCV > SS K SBW aDQaNCMV > DDQ DQbV > SS SW V > SS NCV > DDQ NDQbNCV > SS SAV > SS DQaNCPNCDQbV > SS SAV > SS NCDQaRNCSAM1 > (1) V > (2) DD M2 SANCTNCSA(x18)SANC(x36)SASA(x18)ZZUV > (3) DDQ TMSTDITCKTDORSVD V > DDQ Notes :1. Pad Location 3R is defined as an M1 mode pin in LW SRAMs. However, it must be tied Γlow...

x(t (t OperationDQ(t > n )SW (t > n )SBW > n )G > n )DQ(t > n+1 )X1XXXXSleep (Power Down) ModeHi - ZHi - Z ↑ 01XXXDeselect***Hi - Z ↑ 001X1ReadHi - ZHi - Z ↑ 001X0Read***Q(t > n ) ↑ 0000XWrite All Bytes***D(t > n ) ↑ 000XXWrite Bytes With SBW x = 0***D(t > n ) ↑ 0001XAbort Write***Hi - Z Notes: 1.1Ӕ = input highӔ; 0Ӕ = input lowӔ; XӔ = input donӒt care.2. ԓ*** indicates that the input requirement or output state is determined by the previous operation.3.DQs are tri-stated in response to Write and Deselect commands, one cycle after the command is sampled. > Sleep (power down) mode is provided...

(V > o SS = 0V, T > A = 0 to 85 C) > DD 1.71.81.9V1Output Supply VoltageV > DDQ 1.4---V > DD VInput Reference VoltageV > REF V > DDQ /2 - 0.1V > DDQ /2V > DDQ /2 + 0.1V2Input High Voltage (Address, Control, Data)V > IH V > REF + 0.1---V > DDQ + 0.3V3Input Low Voltage (Address, Control, Data)V > IL -0.3---V > REF - 0.1V4Input High Voltage (M1, M2)V > MIH V > REF + 0.3---V > DD + 0.3VInput Low Voltage (M1, M2)V > MIL -0.3---V > REF - 0.3VClock Input Signal VoltageV > KIN -0.3---V > DDQ + 0.3VClock Input Differential VoltageV > DIF 0.2---V > DDQ + 0.6VClock Input Common Mode VoltageV > CM V > DDQ...

(V > o DD = 1.8V α 0.1V, V > SS = 0V, T > A = 0 to 85 C) > LI V > IN = V > SS to V > DDQ -5---5uAInput Leakage Current (M1, M2)I > MLI V > MIN = V > SS to V > DD -5---5uAOutput Leakage CurrentI V > OUT = V > SS to V > DDQ LO -5---5uAAverage Power Supply Operating CurrentI G = V > IH DD-3 I = 0 mASS ------ --------- ---650600 540mAPower SupplyStandby CurrentI I > OUT DD-33 I > DD-4 = V > IL , ZZ = V > IL I > OUT = 0 mAZZ = V > SB ------180mA1Output High VoltageV > IH I > OH = -6.0 mARQ = 250 > OH V - 0.4------VOutput Low VoltageV Ω > DDQ I > OL = 6.0 mARQ = 250 > OL ------0.4VOutput Driver ImpedanceR...

ItemSymbolConditionsUnitsNotesInput Reference VoltageV > REF 0.75VInput High LevelV > IH 1.25VInput Low LevelV > IL 0.25VInput Rise & Fall Time2.0V/nsInput Reference Level0.75V Clock Input High VoltageV > KIH 1.25VV > DIF = 1.0VClock Input Low VoltageV > KIL 0.25VV > DIF = 1.0VClock Input Common Mode VoltageV > CM 0.75VClock Input Rise & Fall Time2.0V/nsClock Input Reference LevelK/K crossVOutput Reference Level0.75VOutput Load ConditionsRQ = 250 Ω See Figure 1below >

ItemSymbolConditionsUnitsNotesInput Reference VoltageV > REF 0.9VInput High LevelV > IH 1.4VInput Low LevelV > IL 0.4VInput Rise & Fall Time2.0V/nsInput Reference Level0.9V Clock Input High VoltageV > KIH 1.4VV > DIF = 1.0VClock Input Low VoltageV > KIL 0.4VV > DIF = 1.0VClock Input Common Mode VoltageV > CM 0.9VClock Input Rise & Fall Time2.0V/nsClock Input Reference LevelK/K crossVOutput Reference Level0.9VOutput Load ConditionsRQ = 250 ТĦ See Figure 2below >

DummyDummy ReadReadReadReadReadWriteWriteWriteReadRead Read > t > KHKH t > KHKL t > KLKH t > AVKH t > KHAX IL t > WVKH t > KHWX t > WVKH t > KHWX t > GLQV t > GHQZ t > GLQX t > KHQV t > KHQX t > KHQZ t > DVKH t > KHDX t > KHQX1