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Networking High-Speed Synchronous SRAMs CXK79M72C164GB

Networking High-Speed Synchronous SRAMs CXK79M72C164GB

Product catalog summary

Overview: This document provides detailed technical specifications and operational features of Sony's high-speed synchronous SRAMs, specifically the CXK79M72C164GB and CXK79M36C164GB models. These SRAMs are designed for high-performance applications and feature CMOS static RAMs with common I/O pins.

Specifications:

Memory Organization: CXK79M72C164GB is organized as 262,144 words by 72 bits, and CXK79M36C164GB as 524,288 words by 36 bits.
Package: JEDEC-standard 209 pin BGA package.
Operation: Supports Single Data Rate (SDR) Pipelined read operations and Double Late Write (DLW) write operations.
Clock: Positive and negative output clocks for source-synchronous operation.
Speed: Operates at 350 MHz with a single 1.8V power supply.
JTAG: Boundary scan interface using IEEE standard 1149.1 protocol.

Features:

Speed Bins: Options include cycle times of 2.85ns, 3.0ns, 3.3ns, and 4.0ns.
Power Supply: Single 1.8V core power supply with VDDQ ranging from 1.4V to VDD.
I/O Interface: HSTL-compatible with a dedicated input reference voltage (VREF).
Burst Capability: Internally controlled Linear Burst address sequencing with lengths of two, three, or four.
Output Driver Impedance: Programmable via the ZQ control pin.
Depth Expansion: Supported via programmable chip enables.

Operational Details:

Clock Truth Table: Describes logic states for various operations.
State Diagram: Illustrates transitions between operational states.
Burst Operations: Describes sequence and address wrapping.
Depth Expansion: Use of programmable chip enables.
Output Driver Impedance Control: Method for setting impedance using an external resistor.
Power-Up Sequence: Recommended sequence for reliability.

Absolute Maximum Ratings: Lists maximum stress ratings for supply voltage, input voltage, operating temperature, and storage temperature.

Thermal Characteristics: Provides junction to case temperature rating.

I/O Capacitance: Details input and output capacitance under specified test conditions.

Electrical Characteristics:

Supply Voltage: VDD ranges from 1.7V to 1.95V, VDDQ from 1.4V to VDD.
Input Reference Voltage: VREF is VDDQ/2 with a tolerance of ±0.1V.

Procedures:

Guidelines for connecting the CK input clock to VREF.
Conditions for differential input clocks.

Norms and Standards: Adheres to IEEE std. 1149.1 for JTAG Test Access Port and Boundary Scan interface.

Recommendations: For maximum output drive, tie the ZQ pin to VSS; for minimum, leave unconnected or tie to VDDQ.

AC and DC Electrical Characteristics: Includes input and output leakage currents, power supply operating current, and output driver impedance.

Test Conditions: AC test conditions specified for VDDQ at 1.8V and 1.5V.

JTAG Test Mode: Describes TAP controller operations, TAP registers, and timing diagrams.

Figures and Diagrams: Includes timing diagrams for read-write-read operations and TAP controller state diagram.

Ordering Information:

Part numbers include CXK79M72C164GB and CXK79M36C164GB.
Speed options range from 2.85ns to 4.0ns cycle times.

Package Details:

209 Pin BGA package with epoxy resin and copper-clad laminate materials.
Package mass is 1.1g.

Revision History: Includes modifications to electrical characteristics, pin assignments, and new speed bins.

Key Notes:

Some instructions and register codes are reserved for manufacturer use only.
Boundary Scan Register bit order assignments detailed for both x72 and x36 configurations.

Catalog excerpts

Networking High-Speed Synchronous SRAMs CXK79M72C164GB-26

PACKAGE MATERIALTERMINAL TREATMENTTERMINAL MATERIALPACKAGE MASSEPOXY RESINCOPPER-CLAD LAMINATESOLDER1.1g SONY CODEJEITA CODEJEDEC CODEBGA-209P-01P-BGA209-14X22-1.0

Open the catalog to page 26

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