ICX642BKA
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Catalog excerpts

Diagonal 4.5mm (Type 1/4) CCD Image Sensor for NTSC Color Video Cameras ICX642BKA Description The ICX642BKA is an interline CCD solid-state image sensor suitable for NTSC color video cameras with a diagonal 4.5mm (Type 1/4) system. Compared with the conventional product ICX226AK, ICX226AZ, basic characteristics such as sensitivity are improved drastically. This chip features a field period readout system and an electronic shutter with variable charge-storage time. (Applications: Surveillance cameras, etc.) Features High sensitivity (Approximately +6dB over ICX226AK, ICX226AZ) High resolution and low dark current Excellent anti-blooming characteristics Ye, Cy, Mg, and G complementary color mosaic filters on chip Continuous variable-speed shutter function No voltage adjustments (Reset gate and substrate bias need no adjustment.) Supply voltage: 12V Reset gate: 3.3V drive Horizontal register: 3.3V drive Recommended range of exit pupil distance: –20 to –100mm * “Super HAD CCD II” is a trademark of Sony Corporation. The “Super HAD CCD II” is a version of Sony's high performance CCD HAD (Hole-Accumulation Diode) sensor with realized sensitivity (typical) of 1000mV or more per 1μm2 (Color: F5.6/BW: F8 in 1s accumulation equivalent). Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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Device Structure Interline CCD image sensor Image size : Diagonal 4.5mm (Type 1/4) Number of effective pixels : 510 (H) × 492 (V) approx. 0.25M pixels Total number of pixels : 537 (H) × 505 (V) approx. 0.27M pixels Chip size : 4.34mm (H) × 3.69mm (V) Unit cell size : 7.15μm (H) × 5.55μm (V) Optical black : Horizontal (H) direction: Front 2 pixels, rear 25 pixels Vertical (V) direction : Front 12 pixels, rear 1pixel Number of dummy bits : Horizontal: 16 Vertical : 1 (even fields only) Substrate material : Silicon Optical Black Position (Top View) Pin 1 1

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USE RESTRICTION NOTICE This USE RESTRICTION NOTICE (“Notice”) is for customers who are considering or currently using the CCD image sensor products (“Products”) set forth in this specifications book. Sony Corporation (“Sony”) may, at any time, modify this Notice which will be available to you in the latest specifications book for the Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You...

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Block Diagram and Pin Configuration Vertical Register Horizontal Register : Photo sensor Vertical register transfer clock Supply voltage Vertical register transfer clock Vertical register transfer clock Substrate clock Vertical register transfer clock Protective transistor bias Reset gate clock Horizontal register transfer clock Signal output Horizontal register transfer clock

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Absolute Maximum Ratings Item VDD, VOUT, RG – φSUB Against φSUB Potential difference between vertical clock input pins Between input clock pins Operating temperature Storage temperature When the clock width is less than 10μs and clock duty factor is less than 0.1%, voltages up to 20V are guaranteed. Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Reset gate clock For the VL setting, use the VVL voltage of the vertical clock waveform or the same voltage as the VL power supply of the V driver. Do not apply a DC bias to the substrate clock and reset gate clock...

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Clock Voltage Conditions Waveform diagram VφV Vertical transfer clock voltage Readout clock voltage High-level coupling High-level coupling Low-level coupling Low-level coupling Input through 0.1μF capacitance VRGLH – VRGLL Low-level coupling VRGL – VRGLm Horizontal transfer clock voltage Low-level coupling VφRG Reset gate clock voltage Substrate clock voltage

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Clock Equivalent Circuit Constants Item Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistance Vertical transfer clock ground resistance Horizontal transfer clock series resistance Reset gate clock series resistance Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vertical transfer clock equivalent circuit Reset gate clock equivalent circuit Horizontal transfer clock...

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Drive Clock Waveform Conditions 1. Readout clock waveform 100% 90% 2. Vertical transfer clock waveform Vφ1 VVHL VVHL VVHL VVHL

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3. Horizontal transfer clock waveform tr 4. Reset gate clock waveform tr Point A RG waveform VRGLH VRGL VRGLL VRGLm Hφ1 waveform VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 VRGH is the minimum value during the interval twh, VφRG = VRGH – VRGL VRGLm is the negative overshoot level during the falling edge of RG. 5. Substrate clock waveform 100% 90% (Internally generated bias) 0%

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Clock Switching Characteristics Readout clock Vertical transfer clock During a video period Horizontal transfer clock During parallel-to-serial conversion Substrate clock During readout Reset gate clock Unit Remarks When μs draining charge When vertical transfer clock driver CXD1267AN is used. When VφH = 3.0V. tf ≥ tr – 2ns, and the cross-point voltage (VCR) for the Hφ1 rising side of the Hφ1 and Hφ2 waveforms must be at least VφH/2 [V].

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