ICX418ALB Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA B/W Video Cameras Description The ICX418ALB is an interline CCD solid-state image sensor suitable for EIA B/W video cameras with a diagonal 8mm (Type 1/2) system. Compared with the current product ICX038DLB, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically. This chip features a field period readout system and an electronic shutter with variable charge-storage time. Also, this outline is miniaturized by using original package. This chip is compatible with the pins of the ICX038DLB and has the same drive conditions. Features • High sensitivity (+5.0dB compared with the ICX038DLB) 3 • Low smear (–5.0dB compared with the ICX038DLB 40 H Pin 9 • High D range (+2.0dB compared with the ICX038DLB) • High S/N Optical black position • High resolution and low dark current (Top View) • Excellent antiblooming characteristics • Continuous variable-speed shutter • Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V) • Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V) • Horizontal register: 5V drive • Maximum package dimensions: φ13.2mm Device Structure • Interline CCD image sensor • Optical size: Diagonal 8mm (Type 1/2) • Number of effective pixels: 768 (H) × 494 (V) approx. 380K pixels • Total number of pixels: 811 (H) × 508 (V) approx. 410K pixels • Chip size: 7.40mm (H) × 5.95mm (V) • Unit cell size: 8.4µm (H) × 9.8µm (V) • Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels • Number of dummy bits: Horizontal 22 Vertical 1 (even fields only) • Substrate material: Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

USE RESTRICTION NOTICE (December 1, 2003 ver.) This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify this Notice which will be available to you in the latest specifications book for the Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor....

Vertical Register Block Diagram and Pin Configuration (Top View) Note) Horizontal Register : Photo sensor Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Substrate clock Reset drain bias Vertical register transfer clock Reset gate clock Protective transistor bias Substrate bias circuit supply voltage Output circuit supply voltage Horizontal register transfer clock Signal output Horizontal register transfer clock

Absolute Maximum Ratings Item VDD, VRD, VDSUB, VOUT – φSUB Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins Pins other than GND and φSUB – VL Storage temperature Operating temperature Substrate clock φSUB – GND Supply voltage Clock input voltage ∗1 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

Bias Conditions 1 [when used in substrate bias internal generation mode] Item Output circuit supply voltage Reset drain voltage Protective transistor bias Substrate bias circuit supply voltage Substrate clock ∗1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) ∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. Bias Conditions 2 [when used in substrate bias external adjustment mode] Item Output circuit supply voltage...

Clock Voltage Conditions Item Readout clock voltage Waveform diagram VφV Vertical transfer clock voltage High-level coupling High-level coupling Low-level coupling VVLL Horizontal transfer clock voltage Low-level coupling VRGLH – VRGLL Substrate clock voltage VφSUB VRGL Reset gate clock voltage∗1 Low-level coupling ∗1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications. Item Reset gate clock voltage

Clock Equivalent Circuit Constant Symbol Capacitance between horizontal transfer clock CφH1 and GND CφH2 Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Vertical transfer clock series resistor Vertical transfer clock ground resistor Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit

Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% (2) Vertical transfer clock waveform Vφ1 VVHL VVHL VVHL VVHL

(3) Horizontal transfer clock waveform tr (4) Reset gate clock waveform VRGLH VRGL VRGLL VRGLm Hφ1 waveform +2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the period twh, then: VφRG = VRGH – VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform 100% 90%