SP12T + SP9T Antenna Switch Module for 19TRx/2Tx with MIPI I/F for Qualcomm chipset The CXM3642K is a SP12T+SP9T antenna switch module for GSM / UMTS / CDMA / LTE multi-mode handset. The CXM3642K has a +1.8V CMOS compatible decoder with MIPI function for Qualcomm chipset. The Sony GaAs junction gate pHEMT (JPHEMT) MMIC process is used for low insertion loss and high linearity. The device has low BOM with no DC blocking Capacitor. (Applications: GSM/TD-SCDMA/WCDMA/LTE multi-mode handset) High Linearity: CMOS control for serial interface (MIPI I/F for Qualcomm chipset) No DC Blocking Capacitors except sourcing DC bias Small Package Size: Lead-Free and RoHS Compliant Structure GaAs Junction Gate pHEMT (JPHEMT) MMIC Switch, CMOS Decoder This IC is ESD sensitive device. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits

Absolute Maximum Ratings ◆ Supply voltage ◆ Control voltage for MIPI

Block Diagram of SP12T+SP9T Antenna Switch Module with MIPI TRxLB1 TRxLB2 for High Linearity TRxLB3 for High Linearity TRxLB4 for High Linearity TRxLB5 TRxLB6 TRxLB7 TRxLB8 TxLB GaAs JPHEMT Ant-Switch (SP9T) Level Shifter Decoder DC/DC Converter SDATA SCLK CMOS Switch Controller AntHB GaAs JPHEMT Ant-Switch (SP12T) LPF1

Truth Table HB SP12T ( Register 0 ) State Data Bits ANTHB - TxHB ANTLB - TxLB State “L” means a switch “OFF”, state “H” means a switch “ON”.

Bottom Pad:GND

Electrical Characteristics VDD = 2.5 V , Ta = 25 °C Item AntLB - TxLB AntHB - TxHB Insertion Loss

AntLB - TxLB All Ports in Active Paths AntHB - TxHB AntLB - TxLB Attenuation AntHB - TxHB SCLK falling edge to 90% RF in Active Mode Supply Current Inter Modulation Product Pow er in Rx Band

Tx/TRx to Tx/TRx Isolation Matrix (1 of 4) LB SW State

Tx/TRx to Tx/TRx Isolation Matrix (2 of 4) LB SW State

Tx/TRx to Tx/TRx Isolation Matrix (3 of 4) LB SW State

Tx/TRx to Tx/TRx Isolation Matrix (4 of 4) LB SW State

AntHB to Tx/TRx Isolation (1 of 2) LB SW State

AntHB to Tx/TRx Isolation (2 of 2) LB SW State

AntLB to Tx/TRx Isolation (1 of 2) LB SW State

AntLB to Tx/TRx Isolation (2 of 2) LB SW State * Electrical Characteristics are measured with all RF ports terminated in 50 Ω and measured with the recommended circuit. Corresponding Band of GSM Tx(GSM). * 1 Pin = 35 dBm, 824 to 915 MHz (GSM850/900 Tx) * 2 Pin = 32 dBm, 1710 to 1910 MHz (GSM1800/1900 Tx) Corresponding Band of TRx(UMTS/CDMA/LTE) and GSM Rx(GSM). * 3 Pin = 25 dBm, 704 to 787 MHz (Band 13, Band17) * 4 Pin = 10 dBm, 869 to 960 MHz (GSM850/900 Rx) / Pin = 26 dBm, 824 to 960 MHz (Band 5, Band6, Band 8) * 5 Pin = 10 dBm, 1805 to 1990 MHz (GSM180/1900 Rx) / Pin = 26 dBm, 1710 to 1990...

Electrical Characteristics of Triple Beat Ratio VDD = 2.5 V, Ta = 25 °C Condition Item Triple Beat Ratio Triple Beat Product at TRx [MHz] * Electrical Characteristics are measured with all RF ports terminated in 50 Ω and measured with the recommended circuit. Electrical Characteristics of Input IP2 VDD = 2.5 V, Ta = 25 °C Condition * Electrical Characteristics are measured with all RF ports terminated in 50 Ω and measured with the recommended circuit.

MIPI Specification Features PM_TRIG with three triggers Software reset and debug using the RFFE_STATUS register Full speed write, Half speed read Programmable USID Control Characteristics Parameter Supply Voltage Signal level high SCLK write Frequency SCLK read Frequency SDATA/SCLK input capacitance Data setup time Data hold time Supply current (ACTIVE) VDD = 2.5 V Supply current Low Power(disable) VDD = 2.5 V Interface Supply Voltage Supply current (ACTIVE) VIO = 1.8 V Supply current Low Power(disable) VIO = 1.8 V * Turn on time: Time to guarantee RF performance after switch activation.

Explanation of Register Slave Address: 1011 Register Address Register Name Data Bits Read Write HB Antenna sw itch states (see Truth Table) Register 0 Write command sequence use. Trigger Supprt. HB Antenna sw itch states (see Truth Table) Read/Write command sequence use. Trigger Supprt. LB Antenna sw itch states (see Truth Table) Read/Write command sequence use. Trigger Supprt. SOFTWARE RESET SPARE MANUFACTURER_ID USID (Table I)

Write and Read command sequence - REGISTER_0 Write command sequence SCLK Slave Address - Write command sequence (except REGISTER_0) SCLK Slave Address Write Command Register Address - Read command sequence Data frame from ANT Switch needs Half Speed function ① Slave Address Read Command Register Address Data f rame f rom ANT Sw itch (Read Half Speed)

Register Map Table A REGISTER_0 for HB ANT Switch State (0x0000) Command Frame Switch State See the truth table Trigger Supprt. Register Address Table C LB ANT Switch State (0x0001) Command Frame Slave Address Read Write Register Address Data Frame Description Address of Antenna Switch Module Parity bit for Command Frame Switch State See the truth table Trigger Supprt. Parity bit for Data Frame Slave Address Address of Antenna Switch Module Data Frame Slave Address Command Frame Table B REGISTER_0 for HB ANT Switch State (0x0000) Address of Antenna Switch Module Parity bit for Command Frame Switch...

Read Write Register Address Parity Bit Data Frame Items Slave Address Address of Antenna Switch Module Command Frame Command Frame Slave Address Parity bit for Command Frame 0: Normal operation 0/1 1: Software reset (reset of all configurable registers to default values, except for USID、PM_TRIG、GSID) 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Read Write Register Address Parity Bit Command sequence received with parity error – discard command. Command length error Address frame parity error = 1 Data frame with parity error Read command to an invalid address Write command to an invalid address Read command...