CXM3604UR
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Catalog excerpts

High Cap Switchable Step Capacitor (SPI 32-bit) For Antenna Tuning CXM3604UR Description This product has single 5-bit capacitor array with high accuracy. Sony GaAs JPHEMT process is utilized for antenna tuning solution which needs high linearity and high Quality factor. Features ◆ 5 bits resolution Switchable Step Capacitor ◆ High power handling and High linearity ◆ High Q factor and High accuracy capacitor (+/-5 % typ.) ◆ Low insertion loss ◆ Through path ◆ Standby mode (Wakeup time < 40 μs) ◆ Applicable frequency 100 MHz to 3 GHz ◆ SPI 32-bit interface (1.8 V typ.) ◆ Low voltage operation : 2.4 V to 3.3 V ◆ Small package: UQFN-12P (2.2 mm × 2.2 mm × 0.6 mm Max.) ◆ Robustness against ESD ◆ Lead-Free and RoHS Compliant Structure 5 bits Capacitor Array: GaAs Junction Gate pHEMT (JPHEMT) MMIC Driver: CMOS This IC is ESD sensitive device. Special handling precautions are required. 1

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Block Diagram & Pin Configuration

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Truth Table Function Write mode Description Write to the Device Address (Slave Type) Address (Slave Identifer) Address (Slave SPI register) Not Used Standby*1 F1 selected F2 selected F3 selected F4 selected F5 selected F6 selected Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed Fixed *1 Standby Standby bit is for low current operation in SSC disabled in mobile phone. On Standby mode bias voltage for SSC part is shutoff. Regardless of standby and active, IC can receive SPI data during supplying regular voltage to SPI_VDD.

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DC Bias Condition Ta = 25 ˚C Parameter SPI_CLK(H) SPI_DATA(H) SPI_FRM(H) SPI_CLK(L) SPI_DATA(L) SPI_FRM(L) SPI_CLK SPI_DATA SPI_FRM Address bits Data bits Total bits Clock rate Clock edge (data sampling) SPI_FRM tCWL tCWH SPI_CLK SPI_DATA Absolute Maximum Ratings VDD Control Voltage Maximum input power Bias Voltage Operating Temperature Storage Temperature

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Electrical Characteristics Item SPI_Bias current RF pins 50 Ω terminated. No RF power input. SPI_VDD = 1.8 V Time from SPI_VDD, turn on to SPI_FRM H_level Clock frequency Clock cycle SPI_VDD Enable CLK_Freq = 26 MHz Clock begin time Clock width High Data setup time Data hold time Wake-up time SPI_FRM = H, When signal is input. Wake-up time of inside DC-DC converter (VDD On, release standby mode) Active mode, SPI:bit[16] = H Standby mode, SPI:bit[16] = L Active mode, SPI:bit[16] = H Series connection Transmission Performance Shunt connection Electrical Characteristics are measured with all...

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Electrical Characteristics are measured with all RF ports terminated by 50 Ω.

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Series connection Electrical Characteristics are measured with all RF ports terminated by 50 Ω. Shunt connection

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Shunt connection Harmonics under Variable LOAD Series connection Time from falling edge of SPI_FRM to 100 % RF transient power Switching Time

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Series connection Case *1: RF1 and RF2 connecting to signal line. *2: Cbypass = 0.1 μF *3: Inductor value depending on design. DC level of both RF1 and RF2 is GND.

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Shunt connection Case *1: RF1 port connecting to signal line, RF2 port connecting to gnd. DC level of RF1 is GND. *2: Cbypass = 0.1 μF.

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■PKG : 2,2ramx2.2mm * Metal mask "thickness : 110(jm

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Note Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits

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