CXM3580UR
1 /13Pages

CXM3580UR

CXM3580UR
1 /13Pages

Catalog excerpts

CXM3580UR-1

SP4T + SP5T Antenna Switch Module for GSM/UMTS/CDMA/LTE Multi-mode CXM3580UR Description The CXM3580UR is a SP4T+ SP5T antenna switch module for GSM/UMTS/CDMA /LTE multi-mode handset. The CXM3580UR has a built-in dual low pass filter and a +1.8 V CMOS compatible decoder. The Sony GaAs Junction gate pHEMT (JPHEMT) MMIC process is used for low insertion loss and high linearity. The device has low BOM with no DC blocking capacitor. (Application: GSM/UMTS/CDMA/LTE multi-mode handset) Features Low insertion loss: High linearity: Low voltage operation: 0.40 dB (Typ.) TRx (Cellular band) 0.58 dB (Typ.) TRx (IMT Tx band) IIP3 = 68 dBm VDD = 2.5 V UQFN-26P (2.6 mm 3.4 mm 0.625 mm Max.) Lead-free and RoHS compliant Small packing (size): Structure GaAs Junction gate pHEMT (JPHEMT) MMIC switch, CMOS decoder This IC is ESD sensitive device. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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CXM3580UR-2

Absolute Maximum Ratings Control voltage Vctl 4 V Input power max. (Tx1) 36 dBm (Duty cycle = 12.5 % to 50 %) Input power max. (Tx2) 34 dBm (Duty cycle = 12.5 % to 50 %) Operating temperature range -35 to +90 °C Storage temperature range -65 to +150 °C

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CXM3580UR-3

Block Diagram SP4T + SP5T Antenna Switch Module Truth Table SW State (*1) Active Path CTLA CTLB CTLC CTLD State “L” means a switch “OFF”, state “H” means a switch “ON”.

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CXM3580UR-5

Electrical Characteristics (VDD = 2.5 V, Ta = 25 C) Item All ports in Active paths Insertion loss Inter modulation product power in Rx band Switching time Control current Supply current

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CXM3580UR-7

Electrical characteristics are measured with all RF ports terminated in 50 Ω. Corresponding Band of GSM Tx/Rx (GSM). *1 *2 *3 *4 Corresponding Band of TRx (UMTS/CDMA). *5 *6 *7 *8 Pin = 26 dBm, 824 to 960 MHz (Band 5, Band 6, Band 8) Pin = 26 dBm, 1710 to 1990 MHz (Band 1 Tx, Band 2 Tx, Band 4 Tx) Pin = 10 dBm, 2110 to 2170 MHz (Band 1 Rx, Band 4 Rx) Measured with the recommended circuit

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CXM3580UR-9

Triple Beat Ratio (VDD = 2.5 V, Ta = 25 C) Item Triple Beat Ratio Triple Beat Product at TRx*1 [MHz] Electrical characteristics are measured with all RF ports terminated in 50 . Measured with the recommended circuit Electrical characteristics are measured with all RF ports terminated in 50 . Measured with the recommended circuit

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CXM3580UR-10

2. DC levels of all RF ports are GND. 3. L1 (22 nH) and C1 (12 pF) are recommended on Ant port for ESD protection. 4. L2 (12 nH) and C2 (12 pF) are recommended on Ant port for ESD protection. Note) 1. No DC blocking capacitors are required on all RF ports. Recommended Circuit

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CXM3580UR-11

Recommended Land Pattern Metal mask thickness: 110 µm Pin pitch: 0.4 mm Mask (Open area) Metal area in board (∗1) ∗1: GND plane is recommended Resist (Open area)

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CXM3580UR-12

Package Outline TERMINAL SECTION ^□te:Termi nal burr height 0.05mm MAX ) LPT NO. I HAY 3 CHARAPTERS : SERIAL CODE I IN SECTION B ( FOLLGtf RULES FOR ABBBEVI AT I DNS._ A YEAR COPE I THE 2ND BIT OF A BINARY STSTEN BIT SYSTEM IS DISPLAYED IN I A YEAR COPEI TDE 3RD BIT OF A BINARY SYSTEM BIT SYSTEM IS DISPLAYEP IN I A YEAR COPE ( TDE 4TD BIT OF A BINARY SYSTEM BIT SYSTEM IS PISPLAYEP IN I 1) TYPE HP. I MAY 5 CHARACTERS I IN SECTION C._ I FOR HERE TDAH 5 PDARAPPERS FOLLOW RULES FOR ABBREVIATIONS. I_ 31 ASSEMBLY PLACE IN SECYIOH e.

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CXM3580UR-13

Packag Outline SERIAL CODE I IH SECTION B HftNUFACTURING VEAR IS DISPLft'VED BY f 111 11)'*1 INC HfN.'.Rf HI I SYSTEM. )_ ft YEAR CODE! THE 1ST BIT DF A BINARY SYSTEM BIT SIS 11H IS DISPLAYED IN I DOT ) IH SECTION a. ft YEAR CODE ( TBE 2ND BIT DF ft BINART SYSTEM BIT SYSIIH IS DISPLAYED IN I DOT )IN SECT I ON b. ft f EAR CODE ( THE 3RD BIT DF ft BINARY SYSTEM BIT SYSTEM IS DISPUTED IN I DOT ) IN SECTION c. ft TEAR CODE ( THE 4TH BIT DF ft BINARY SYSTEM HIT SYSTEM IS DISPLAYED IN I DOT ) IN SECTION A. ( FOR HO-E I \----:~lzi FOLLOW ROLES FOB ABBREmilQKS !_ Sony Corporation

 Open the catalog to page 13

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*Prices are pre-tax. They exclude delivery charges and customs duties and do not include additional charges for installation or activation options. Prices are indicative only and may vary by country, with changes to the cost of raw materials and exchange rates.