SP4T + SP6T Antenna Switch Module for 6TRx/2Tx/2Rx with SPI I/F CXM3580AUR Description The CXM3580AUR is a SP4T+ SP6T antenna switch module for GSM/UMTS/CDMA /LTE multi-mode handset. The CXM3580AUR has a +1.8 V CMOS compatible decoder with SPI function. The Sony GaAs junction gate pHEMT (JPHEMT) MMIC process is used for low insertion loss and high linearity. The device has low BOM with no DC blocking Capacitor (Application: GSM/UMTS/CDMA/LTE Multi-mode Handsets) Features Low insertion loss: 0.37 dB (Typ.) TRx (Cellular band) 0.95 dB (Typ.) TRx (IMT Tx band) High linearity: IIP3 = 68 dBm Low voltage operation: VDD = 2.5 V Supports CMOS control for serial interface No DC blocking capacitor Small packing (size): UQFN-26P (2.6 mm 3.4 mm 0.625 mm Max.) Lead-free and RoHS compliant Structure GaAs Junction gate pHEMT (JPHEMT) MMIC switch, CMOS decoder This IC is ESD sensitive device. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Absolute Maximum Ratings Bias voltage Operating temperature range Storage temperature range

Block Diagram SP4T + SP6T Antenna Switch Module with SPI Level shifter DC-DC Converter CMOS Switch Controller

Truth Table SW State (*1) Active Path State “L” means a switch “OFF”, state “H” means a switch “ON”. State “Idle” means that the DC/DC converter is “OFF”, and the switch paths are in an undefined state.

DC Bias Conditions (Ta = 25 C) Item

Electrical Characteristics (VDD = 2.5 V, Ta = 25 C) Item All ports in Active paths Insertion loss Inter modulation product power in Rx band Switching time Supply current Active or Isolation mode Idel mode

Electrical characteristics are measured with all RF ports terminated in 50 Ω. Corresponding Band of GSM Tx/Rx (GSM). *1 *2 *3 *4 Corresponding Band of TRx (UMTS/CDMA). *5 *6 *7 *8 Pin = 26 dBm, 824 to 960 MHz (Band 5, Band 6, Band 8) Pin = 26 dBm, 1710 to 1990 MHz (Band 1 Tx, Band 2 Tx, Band 4 Tx) Pin = 10 dBm, 2110 to 2170 MHz (Band 1 Rx, Band 4 Rx) Measured with the recommended circuit

Triple Beat Ratio (VDD = 2.5 V, Ta = 25 C) Item Triple Beat Ratio Triple Beat Product at TRx* [MHz] * Electrical characteristics are measured with all RF ports terminated in 50 . Measured with the recommended circuit * Electrical characteristics are measured with all RF ports terminated in 50 . Measured with the recommended circuit

Clock freaquency SPI_VDD Enable Clock cycle Clock begin time Clock width High Data setup time Data hold time SPI_VDD rise time TSPI_VDD Rise

SPI Control Specification Item Address bits Data bits Total bits Clock edge (data sampling) Specification 14 bits 16 bits 30 bits total Rising edge Control Data * Either idle state D11 to D14 is 0000, or XXXX. Clock Block Diagram FRM CLK

Recommended Circuit Note) 1. No DC blocking capacitors are required on all RF ports. 2. DC levels of all RF ports are GND. 3. L1 (22 nH) and C1 (12 pF) are recommended on Ant port for ESD protection. 4. L2 (12 nH) and C2 (12 pF) are recommended on Ant port for ESD protection. 5. C3 capacitor (100 pF) is recommended.

Recommended Land Pattern Metal mask thickness: 110 µm Pin pitch: 0.4 mm : Metal area in board (∗1) ∗1: GND plane is recommended : Mask (Open area) : Resist (Open area)

Package Outline Note :Term i na I burr height 0. 0 5mm MAX. = SERIAL CODE ) IH SECTION 0._ I FOLLOW BOLES FOR ftflBBEVI ftTI ONS._ HftNU FACTURI NG YEAR IS [IISPLfilEO BY FOLLOWING BYHARY BIT SYSTEM. )_ ft YEAR C00EI TIE I ST BIT OF ft BI MARY SYSTEM BIT SYSTEM IS □ I SPLAYED IN 1 DOT I IN SECTION a ft YEAR CODE! TIE 2ND BIT OF ft BI MARY SYSTEM PIT SYSTEM IS 01 SPLAYED IN I OPT ) IN SECTION i ft YEAR CODE [ TIE 3RD BIT OF ft BINARY SYSTEM BIT SYSTEM IS 0ISPLAYED IN 1 DOT ] IN SECTION c ft YEAR COOEl TIE 4TB BIT OF ft BINARY SYSTEM BIT SYSTEM IS DISPLAYED IN I DOT ] IN SECTION J H TYPE NO. {...

Package Outline TERMINAL SECTION Note:Terrni nal burr height 0. 0 5mm MAX. jH]-r i2m\z<j yntmav hBts*) imt&a_ 1) LOT IIP. ( MS) 3 CHARACTERS : 5 E RI AL CODE ) IN SECTION I._ ( FOLLOW RULES FOB ABBREVI AT IQNB-_ MANUFACTURING- f EAR 15 0ISPLAYEP 01 FPL LOW IH & BYNARf PIT SYSTEM. )_ A VEftR C0DE1 THE 1ST PIT OF A 01 NARY SYSTEM BIT SYSTEM IS DISPLAYED IN I POT I IN SECTION a A YEAR CODE! THE 2ND 0 IT OF A 01 NARY SYSTEM BIT SYSTEM IS DISPLAYED IN I PPT )IN SECTION b A YEAR C0DE1 TPE 3RD PIT OF A PINARY SYSTEM BIT SYSTEM IS DISPLAYED IN I POT ) IN SECTION c A fEAR CODE! TPE 4TH PIT OF A PINARY...