SP4T Antenna Switch for GSM / CDMA / UMTS CXM3569XR Description The CXM3569XR is a high power SP4T antenna switch for GSM / CDMA / UMTS applications. The antenna port can be routed to either of the 4TRx ports. The low insertion loss on transmit means increased talk time as the Tx power amplifier can be operated at a lower output level. Built-in decoder reduces component count and simplifies PCB layout by allowing direct connection of the switch to digital base band control lines with the 1.8 V CMOS logic levels. The Sony GaAs JPHEMT MMIC Process is used for low insertion loss and high linearity. Features ◆ Low Insertion Loss: 0.31 dB typical (Cellular / GSM Low Band) 0.41 dB typical (PCS / GSM High Band) 0.46 dB typical (IMT2000) ◆ No DC Blocking Capacitors Required on RF ports. ◆ Small Package Size: ◆ Lead-Free and RoHS Compliant Structure GaAs JPHEMT MMIC Absolute Maximum Ratings ◆ Bias Voltage ◆ Maximum input power ◆ Storage Temperature ◆ Maximum power dissipation ◆ Copper-clad lamination of glass board(4 layer) *NOTICE Please use this product without exceeding PD value showed on it's specification. If it is used with exceeding PD value even for a moment, there are possibilities of degradation or breakdown because of the heat generated by product operation. GaAs MMICs are ESD sensitive devices. Special handling precautions are required.

Block Diagram CMOS Decoder Block Diagram of RF Switch

Truth Table ON Path CTLA ANT – RF1 L ANT – RF2 H ANT – RF3 L ANT – RF4 H Parameter Vdd Vctl(H) Vctl(L)

Electrical Characteristics 1 Vdd = 2.5 V, Vctl = 0/1.8 V Ta = 25 °C Electrical Characteristics are measured with all RF ports terminated in 50 Ω. *1 *2 *3 *4 freq = 698 to 960 MHz freq = 1710 to 1990 MHz freq = 2110 to 2170 MHz freq = 2500 to 2690 MHz

Electrical Characteristics 2 Vdd = 2.5 V, Vctl = 0/1.8 V Ta = 25 °C Item VSWR P0.2dB Compression Inter Modulation Product Power in Rx Band Control Current Supply Current Switching Time Wakeup Time 824 to 1980 MHz *5 -*8, *15 *9 -*12, *15 *13, *15 *14, *15 Vctl = 1.8 V per line Vdd = 2.5 V 50 % Ctl to 90 % RF Wakeup time from Vdd on to Active mode Electrical Characteristics are measured with all RF ports terminated in 50 Ω. Corresponding Band of TRx (UMTS/CDMA) *1 *2 *3 *4 *5 *6 *7 *8 *9 * 10 * 11 * 12 * 13 * 14 * 15 Pin = 35 dBm, freq = 824 to 915 MHz Pin = 32 dBm, freq = 1710 to 1910 MHz Pin...

Electrical Characteristics 3 Vdd = 2.5 V, Vctl = 0/1.8 V Ta = 25 °C Item Symbol Triple Beat Ratio Triple Beat Product at RF* [MHz] 881.5±1 1960±1 2132±1 Electrical Characteristics are measured with all RF ports terminated in 50 Ω. Measured with the recommended circuit Electrical Characteristics 4 Vdd = 2.5 V, Vctl = 0/1.8 V Ta = 25 °C Item Symbol Electrical Characteristics are measured with all RF ports terminated in 50 Ω. Measured with the recommended circuit

Recommended Circuit 1: No DC blocking capacitors are required on all RF ports. *2: DC levels of all RF ports are GND. *3: L1(39 nH) and C1(15 pF) are recommended on Ant port for ESD protection. *4: C2(100 pF) is recommended on Vdd pin for Decoupling Capacitor.

Recommended Land Pattern XQFN-20P-02 Macro for MMIC ・PKG Size□2.5mm×t0.35mm ・Terminal Pitch0.4mm :Land area :Board resist open area :Mask open area (Solder printing area) :Metal area in board (*1)

aSfi$3- K (2 l;£b-y h 7^(7)1 b'7 hgfrj^) frEMTS. bSEfrJ - K (2il£b''y hfiafl2b'-y hBft&iO EElta. I) LOT NO. I Ut 3 CHARACTERS ■ SERIAL CODE ) IN SECTION B,_ [ FOLLOW RULES FOB ABBREVIATIONS._ MANUFACTURING YEAR IS DISPLAYED BY FOLLOW ING BYNARY BIT SYSTEM. ) A YEAR CODE I THE 1ST BIT OF A BINARY SYSTEM BIT SYSTEM IS DISPLAYED IN I DOT )IN SECTION a. A YEAR CODEI THE 2ND BIT OF A BINARY SYSTEM BIT SYSTEM IS DISPLAYED IN I DOT )IN SECTION b. A YEAR CODE ( THE 3RD BIT OF A BINARY SYSTEM BIT SYSTEM IS DISPLAYED IN I DOT )IN SECTION c. A YEAR CODE I THE 4TH BIT OF A BINARY SYSTEM BIT SYSTEM IS DISPLAYED...

agEgD- (21£tf-vl-J)ji^1 b'-^B*^) £KITj>. II LOT NO. ( MAX 3 CHARACTERS ■ SERIAL CODE ) IN SECTION 8._ I FOLLOW RULES FOR ABBREVIATIONS._ KAKUFACTURING YEftR IS DISPLACED BY FDLLOWIHC BYNARY BIT SY5TEH. ) A YEfiR CO0EI THE 1ST BIT 3T A BINARY SYSTEM BIT SYSTEM IS DISPLACED IN I OPT TIN SECTION a. A YEAR CODEI THE 2ND BIT OF A BINARY SYSTEM BIT SYSTEM IS DISPLAYED III I OPT TIN SECTION t. A 1EAR CODE! THE 3RD BIT Of A BINARY SYSTEM BIT SYSTEM IS DISPLACED IN I DOT TIN SECTION c. A YEAR CODE I TIE 4TH BIT OF A BINARY SYSTEM BIT SYSTEM IS DISPLACED IN I DOT TIN SECTION d. 21 TYPE NO. I HAY 1 CHARACTERS...

Note Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits