SP5T+ SP5T SOI Antenna Switch with MIPI Interface for Qualcomm chipset CXA4420GC Description CXA4420GC is the SP5T+SP5T antenna diversity switch for WCDMA/3G/LTE applications. CXA4420GC has a 1.8 V CMOS compatible decoder with Qualcomm chipset. The SONY Silicon On Insulator (SOI) technology is used for low insertion loss. Features ◆Low Insertion loss : 0.35 dB (typ.) @800 MHz 0.55 dB (typ.) @2 GHz 0.65 dB (typ.) @2.7 GHz ◆High Isolation : 28 dB (typ.) @2.7 GHz ◆No DC Blocking Capacitors (except sourcing DC bias) ◆Supports CMOS control for serial interface (MIPI I/F for Qualcomm chipset) ◆Solder Bump Bare Die(SBBD): Bump Pitch = 0.4 mm ◆Small Flip-Chip Size : 1.5 mm x 2.3 mm x 0.35 mm Typ. ◆Lead-Free and RoHS compliant ◆Applications: Diversity Switch. Structure SOI CMOS MMIC This IC is ESD sensitive device. Special handling precautions are required

Block Diagram

Truth Table USID=0b1010 (SSEL = L) or 0b1011 (SSEL = H) *ANT1 side Series and ANT1 side Shunt ”L” means a switch “OFF”, ANT1 side Series and ANT1 side Shunt ”H” **ANT2 side Series and ANT2 side Shunt ”L” means a switch “OFF”, means a switch “ON” ANT2 side Series and ANT2 side Shunt ”H”

Absolute Maximum Ratings ◆ Supply voltage ◆ Control voltage (MIPI) ◆ Maximum input ◆ Operating temperature DC Bias Condition ( Ta = 25 ℃) Parameter Supply Voltage Interface Supply Voltage SSEL Supply Voltage low SSEL Supply Voltage High Signal level low Signal level high SCLK write Frequency VDD VIO VSSEL_L VSSEL_H Ccl Vch fSCLKw SCLK read Frequency

Insertion Loss Inter Modulation Distortion in Rx Band Control Current Supply Current Ivio SDATA,SCLK Active Mode Low Power Mode Active Mode Switching Time From Low Power Mode to Active Mode Electrical Characteristics are measured with all RF ports terminated in 50 Ohms. * 1 freq = 704 MHz to 787 MHz * 2 freq = 824 MHz to 960 MHz * 3 freq = 1710 MHz to 2170 MHz * 4 freq = 2500 MHz to 2690 MHz * 5 Pin = 26 dBm, freq = 824 MHz to 915 MHz * 6 Pin = 26 dBm, freq = 1710 MHz to 1910 MHz * 7 Pin = 26 dBm, freq = 2500 MHz to 2570 MHz * 8 Measured with the recommended circuit * 9-20 Refer to the table...

Active path Electrical Characteristics are measured with all RF ports terminated in 50 Ohms. * 21 ANT2 Side is fixed State7 (Isolation) .

Active path Electrical Characteristics are measured with all RF ports terminated in 50 Ohms. * 21 ANT2 Side is fixed State7 (Isolation) .

Active path Electrical Characteristics are measured with all RF ports terminated in 50 Ohms. * 22 ANT1 Side is fixed State1 (Isolation) .

Active path Electrical Characteristics are measured with all RF ports terminated in 50 Ohms. * 22 ANT1 Side is fixed State1 (Isolation) .

Electrical Characteristics are measured with all RF ports terminated in 50 Ohms. * 21 ANT2 Side is fixed State7 (Isolation) . * 22 ANT1 Side is fixed State1 (Isolation) .

SSEL Specification SSEL (Slave Address) MIPI Specification Supply Voltage Supply current (ACTIVE) *VDD = 2.5 V Supply current Low Power(disable) *VDD = 2.5 V Interface Supply Voltage Supply current (Active) *Vio = 1.8 V Supply current Low Power(disable) *Vio = 1.8 V Signal level high SCLK write Frequency SCLK read Frequency SDATA/SCLK input capacitance Data setup time Data hold time Switching Time* * Switching Time: Timing for switching from an arbitrary state to the next state. ** Turn on time: Time to guarantee RF performance after switch activation.

Explanation of Register ・PM_TRIG with three triggers ・Software reset and debug using the RFFE_STATUS register ・Register_0 write ・Full speed write, half speed read ・Extended Read/Write Not Available ・GSID* ・Programmable USID Slave Address : 0b1010 (SSEL = L) or 0b1011 (SSEL = H) Register D0 Register 0 write Command Switch state *See truth table Ant2-RF6toRF10 Switch State Trigger Support. Switch state *See truth table Ant1 side Antenna Switch State Trigger Support. Ant2 side Antenna Switch State Trigger Support. [D7]: SOFTWARE_RESET [D6]: COMMAND_FRAME_PARITY_ERR [D5]: COMMAND_LENGTH_ERR RFFE...

- REGISTER_0 Write command Sequence Slave Address Slave Address Wrte Conmand RegEter Address Slave Address Read Gsrrmand Register Address Data frame from ANT Sw itch (Read Half Speed)

Register Table Table A REGISTER_0 for ANT Switch State (0x0000) Items Sequence Start Condition Data Frame Slave Address Write/Read Command Address of Diversity Switch = 0b1010 (SSEL = L) or 0b1011 (SSEL = H) REGISTER_0 Write : 0b1 Parity bit for Data Frame Table B REGISTER_0 for ANT1 Switch State (0x0000) Items Sequence Start Condition Command Frame Slave Address Write/Read Command Register Address Data Frame Address of Diversity Switch = 0b1010 (SSEL = L) or 0b1011 (SSEL = H) Parity bit for Command Frame [D7:D3] = 0b00000 (Fixed) Initial value : [D7:D0] = 0b0000 0000 Switch State (See the truth...

Table C ANT2 Switch State (0x0001) Items Command Frame Slave Address Write/Read Command Register Address Data Frame Sequence Start Condition Address of Diversity Switch = 0b1010 (SSEL = L) or 0b1011 (SSEL = H) Parity bit for Command Frame [D7:D3] = 0b00000 (Fixed) Initial value : [D7:D0] = 0b0000 0000 Switch State (See the truth table) Trigger support Parity bit for Data Frame Table D RFFE_STATUS (0x001A) Items Sequence Start Condition Command Frame Slave Address Write/Read Command Register Address Data Frame Address of Diversity Switch = 0b1010 (SSEL = L) or 0b1011 (SSEL = H) Parity bit for...

Table E Group Slave ID (0x001B) Items Sequence Start Condition Command Frame Slave Address Write/Read Command Register Address Data Frame Address of Diversity Switch = 0b1010 (SSEL = L) or 0b1011 (SSEL = H) Write : 0b010 Read : 0b011 Parity bit for Command Frame Parity bit for Data Frame Table F Power Mode & Trigger Mode (0x001C) Items Command Frame Slave Address Write/Read Command Register Address Data Frame Sequence Start Condition Address of Diversity Switch = 0b1010 (SSEL = L) or 0b1011 (SSEL = H) Parity bit for Command Frame PWR_MODE[1:0] (R/W) 0b00 : Normal operation (ACTIVE) 0b01: Default...