SP6T SOI Antenna Switch with MIPI Interface for Qualcomm chipset CXA4416GC Description The CXA4416 is the SP6T antenna diversity switch for WCDMA/3G/LTE applications. The CXA4416 has a 1.8V CMOS compatible decoder with MIPI function for Qualcomm chipset. The SONY Silicon On Insulator (SOI) technology is used for low insertion loss. Features ◆Low Insertion loss : 0.40 dB(typ.) @800 MHz 0.50 dB(typ.) @2 GHz 0.54 dB(typ.) @2.7 GHz ◆No DC Blocking Capacitors (except sourcing DC bias) ◆Solder Bump Bare Die (SBBD): Bump Pitch=0.4 mm ◆Supports CMOS control for serial interface(MIPI I/F for Qualcomm chipset) ◆Small Flip-Chip Size : 1.5 mm x 1.5 mm x 0.35 mm Typ. ◆Lead-Free and RoHS compliant ◆Applications: Diversity Switch Structure SOI CMOS MMIC This IC is ESD sensitive device. Special handling precautions are required

Block Diagram Truth Table Active Path MIPI data bits (*1)State "L" means a switch "OFF", State "H" means a switch "ON"

Absolute Maximum Ratings ◆ Supply voltage ◆ Control voltage (MIPI) DC Bias Condition ( Ta=25℃) Parameter Supply Voltage Interface Supply Voltage Signal level high SCLK Frequency (Write) SCLK Frequency (Read)

Idle Mode Idle Mode VSWR Harmonics Inter Modulation Distortion in Rx Band Sw itching Time Wake up Time Tw Control Current Supply Current All ports in active paths ANTRF1,2,3,4,5,6 ANTRF1,2,3,4,5,6 ANT*8,*9,*10,*13,*14, RF1,2,3,4,5,6 *17,*18 *8,*11,*12,*15,*16 ,*19,*20 50% Ctl to 90% RF from idle mode to active mode Active Mode Electrical Characteristics are measured with all RF ports terminated in 50 Ohms. * 1 Pin = 25 dBm, 704 to 787 MHz (Band13, Band17) * 2 Pin = 26 dBm, 824 to 960 MHz (Band5, Band8) * 3 Pin = 26 dBm, 1428 to 1990 MHz (Band1 Tx, Band 2 Tx, Band 3 Tx, Band 4 Tx, Band11 Tx) *...

IIP3 Condition Band Band 1 Band 5

Electrical Characteristics 4 Ant to RF Isolation Matrix Active

MIPI Specification Parameter Supply Voltage Supply current (ACTIVE) *Vdd=2.8V Supply current Low Power(disable) *Vdd=2.8V Interface Supply Voltage Supply current (ACTIVE) *Vio=1.8V Supply current Low Power(disable) *Vio=1.8V Signal level high SCLK write Frequency SCLK read Frequency SDATA/SCLK input capacitance Data setup time Data hold time Switching Time * * Switching Time: Timing for switching from an arbitrary state to the next state. **Turn on time: Time to guarantee RF performance after switch activation.

・Explanation of Register Features: • PM_TRIG with three triggers • Software reset and debug using the RFFE_STATUS register • Register 0 write • Full speed write, half speed read • GSID • Programmable USID Slave Address : 1010 Register Address Register Name Data Bits Read Write Antenna switch states (see Truth Table) Register 0 Write command sequence use. Trigger Supprt. Antenna switch states (see Truth Table) Read/Write command sequence use. Trigger Supprt. SOFTWARE RESET GROUP_ID (Table D) PM_TRIG (Table E) PRODUCT_ID (Table F) MANUFACTURER_ID (Table G) SPARE MANUFACTURER_ID USID (Table H) Power...

・Write and Read Command sequence - REGISTER_0 Write command sequence SCLK Slave Address ・Write command sequence SCLK Slave Address Write Command Register Address ・Read command sequence Data frame from ANT Switch needs Half Speed function. ① Slave Address Read Command Register Address Data frame from ANT Sw itch (Read Half Speed)

・Register Map Register 0 Write command sequence use. 15 Slave Address Read/Write command sequence use. 24 Slave Address Register Address A Frame shall end with a single parity bit. The parity bit shall be driven such that the total number of bits in the Frame that are driven to logic level one, including the parity bit, is odd.

Table A REGISTER_0 for ANT Switch State (0x0000) Command Frame Slave Address Items Slave Address Address of Diversity Switch REGISTER_0 Write : 1 Switch State See the truth table Trigger Supprt. Read Write Register Address Parity Bit Data Frame Command Frame Table B REGISTER_0 for ANT Switch State (0x0000) Description Address of Diversity Switch Parity bit for Command Frame Switch State See the truth table Trigger Supprt. Parity bit for Data Frame Table C RFFE_STATUS (0x001A) Items Command Frame Slave Address Read Write Register Address Data Frame Description Bit SA3 1 SA2 0 Address of Diversity...

Command Frame Slave Address Read Write Register Address Parity Bit Data Frame Table E Power Mode & Trigger Mode (0x001C) Command Frame Slave Address Read Write Register Address Data Frame Register Address Parity Bit Initial value : [D7:D6] =10 Initial value : [D5:D3] =000 Initial value : [D5:D3] =000 Read Write Slave Address Command Frame Data Frame Address of Diversity Switch Read Only Parity bit for Command Frame Parity bit for Data Frame

Table G Manufacturer ID (0x001E) Items Table H Manufacturer ID and USID (0x001F) Description Slave Address Address of Diversity Switch Command Frame Command Frame Register Address Read Write Slave Address Read Only Register Address: 0x001E Parity bit for Command Frame Read Write Register Address Parity Bit Data Frame Data Frame SPARE 1 Manufacturer ID [7:0]:B0h (SONY ID) 1 0 0 0 0 0 Parity bit for Data Frame 0 Manufacturer ID [9:8]:01h (SONY ID) 1 0/1 Initial 0/1 Programmable USID value:[D3:D0] 0/1 =1010 0/1 0/1 Parity bit for Data Frame For Programmable USID The PRODUCT_ID and the MANUFACTURER_ID...

Recommended Circuit *1: No DC blocking capacitors are required on all RF ports. *2: DC levels of all RF ports are GND. *3: L1 (27 nH) and C1 (12 pF) are recommended on Ant port for ESD protection. *4: C2(100 pF) is recommended on VDD pin for Decoupling Capacitor. *5: C3(0.1 uF) is recommended on VIO pin for Decoupling Capacitor.

Solder Bump Foot Print (Macro) *Reference Device specification •Device size : 1.5mm × 1.5mm × t 0.35mm •Pin counts : 14 Pin •Solder Bump height : 0.15mm •Solder Bump ball size : φ0.2mm •Solder Bump pitch : 0.4mm Unit:mm Detail - A •Land size (Resist Open area) : φ200um •Cu pattern size : (φ300um) : Cu pattern 0.4 Index of device : Resist open : Solder print area (Metal mask thickness : 110um)