CXA3197R
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Catalog excerpts

CXA3197R - 1

CXA3197R 10-bit 125MSPS D/A Converter Description The CXA3197R is a high-speed D/A converter which can perform multiplexed input of two system 10-bit data. This IC realizes a maximum conversion rate of 125MSPS. Multiplexed operation is possible by inputing the 1/2 frequency-divided clock or by halving the frequency of the clock internally with the clock frequency divider circuit having the reset pin. The data input is at TTL level, and the clock input and reset input can select either TTL or PECL level according to the application. 48 pin LQFP (Plastic) LEAD TREATMENT: PALLADIUM PLATING Structure Bipolar silicon monolithic IC DGND2 C2 C1 C3 DVCC2 AVCCO Applications • LCD • DDS • HDTV • Communications (QPSK, QAM) • Measuring devices AOUTN AGND2 VREF VSET AVCC2 Pin Configuration AOUTP Features • Maximum conversion rate: During PECL operation: 125MSPS During TTL operation: 100MSPS • Resolution: 10 bits • Low power consumption: 480mW (typ.) • Data input level: TTL • Clock, reset input level: TTL and PECL compatible • 2:1 multiplexed input function • 1/2 frequency-divided clock output possible by the built-in clock frequency divider circuit • Voltage output (50Ω load drive possible) • Single power supply or ±dual power supply operation • Reset signal polarity switching function 36 35 34 33 32 31 30 29 28 27 26 25 AGND2 37 24 RESETN/E VOCLP 38 23 RESETP/E 22 RESET/T R POLARITY 39 INV 40 21 CLKN/E PS 41 20 CLKP/E 19 CLK/T DVCC1 42 18 N.C. 43 DIV2OUT 17 DIV2IN DGND1 44 16 DB0 (LSB) (MSB) DA9 45 DA8 46 15 DB1 8 9 10 11 12 DB4 DA1 7 DB5 DA2 6 DB6 5 DB7 4 DB8 3 (LSB) DA0 2 (MSB) DB9 1 DA3 13 DB3 DA4 14 DB2 DA6 48 DA5 DA7 47 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E97639B22-PS

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CXA3197R - 2

CXA3197R Absolute Maximum Ratings (Ta = 25°C) • Supply voltage AVCCO, AVCC2, DVCC2 AGND2, DGND2 DVCC1 AVCC2 – AGND2 AVCCO – AGND2 DVCC2 – DGND2 –0.5 to +6.0 –6.0 to +0.5 –0.5 to +6.0 –0.5 to +6.0 –0.5 to +6.0 –0.5 to +6.0 V V V V V V • Input voltage (Analog) (Digital) VSET AGND2 – 0.5 to AVCC2 + 0.5 V V TTL input pin DGND1 – 0.5 to DVCC1 + 0.5 PECL input pin DGND1 – 0.5 to DVCC1 + 0.5 V PS DGND1 – 0.5 to DVCC1 + 0.5 V (Others) VOCLP DGND1 – 0.5 to DVCC1 + 0.5 V • Storage temperature Tstg – 65 to +150 °C • Allowable power dissipation Pd 1.4 W (when mounted on a two-layer glass fabric base...

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CXA3197R - 3

CXA3197R Pin Description [ Typical voltage level for a single power supply [Symbol] [Pin No.] [Description] DA0 to DA9 DB0 to DB9 DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E DGND2 C1 C2 C3 DVCC2 AVCCO AOUTN AOUTP AGND2 VREF VSET 1 to 6, 45 to 48 7 to 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Side A data input. TTL Side B data input. TTL 1/2 frequency-divided clock input. TTL 1/2 frequency-divided clock output. TTL TTL clock input. TTL PECL clock input. PECL PECL clock input. PECL TTL reset input. TTL PECL reset input. PECL PECL reset input. PECL Digital...

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CXA3197R - 5

CXA3197R Pin Description and I/O Pin Equivalent Circuit Pin No. Symbol 1 to 6 45 to 48 DA0 to DA9 I/O Typical voltage level I Equivalent circuit TTL Description Side A data input. DVCC1 1 to 6 45 to 48 7 7 to 16 DB0 to DB9 I TTL to 16 1.5V DGND1 Side B data input. DVCC1 17 DIV2IN I TTL 17 1.5V DGND1 DVCC1 DIV2OUT O 18 TTL 100K 18 DGND1 1/2 frequency-divided clock input. Use this pin in MUX.1A or MUX.2 mode. Leave open for other modes. 1/2 frequency-divided clock output. The 1/2 frequencydivided clock signal (DIV2OUT) is output in MUX.1A mode. Set to high impedance for other modes. DVCC1 19...

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CXA3197R - 6

CXA3197R Pin No. Symbol I/O Typical voltage level Equivalent circuit Description Clock input. Use this pin when the clock is input at PECL level. At this time, leave Pin 19 open. CLKP/E and CLKN/E are complementary and should be used together. DVCC1 20 CLKP/E I PECL 20 21 DGND1 21 CLKN/E I CLKP/E complementary input. PECL DVCC1 22 RESET/T I TTL 22 1.5V DGND1 23 RESETP/E I PECL DVCC1 23 24 24 RESETN/E I PECL DGND1 Single power supply: GND Dual power supply: –5V 25 DGND2 26 C1 I TTL 27 C2 I TTL Digital power supply. Function setting. DVCC1 26 Function setting. 27 28 28 C3 I TTL Reset signal...

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CXA3197R - 7

CXA3197R Pin No. 29 30 Symbol I/O Typical voltage level Equivalent circuit Description Single power supply: +5V Dual power supply: GND AVCCO Digital power supply. Single power supply: +5V Dual power supply: GND DVCC2 Analog output power supply. The AVCCO pin voltage can be varied within the range that satisfies the analog output compliance voltage. AVCCO – VFS Negative analog output. The inverse of the positive analog output pin is output. When the positive output is terminated with 50Ω, the inverse output pin should also be terminated with 50Ω even if the inverse output is not used. AVCCO...

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CXA3197R - 8

CXA3197R Pin No. 37 Symbol I/O Typical voltage level Equivalent circuit Description Single power supply: GND Dual power supply: –5V AGND2 Analog power supply. Clamp voltage TTL output High level clamp. A TTL level signal is output from the DIV2OUT pin in MUX.1A mode. The TTL High level voltage can be clamped to the value approximately equivalent to the voltage applied to this pin. Leave the VOCLP pin open for other modes. DVCC1 38 VOCLP I 38 DGND1 DVCC1 39 R POLARITY I TTL 39 1.5V Reset signal polarity switching. At High level, the reset polarity is active Low; at Low level, active High....

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CXA3197R - 9

CXA3197R Electrical Characteristics (DVCC1, DVCC2, AVCC2, AVCCO = +5V, DGND1, DGND2 = 0V, Ta = 25°C) Item Symbol Resolution DLE Integral linearity error Typ. Max. Unit 10 n Differential linearity error Min. Conditions 10 10 bit –0.85/+0.5 –1.2/+0.5 ±1.2 LSB LSB LSB DVCC1 – 0.5 DVCC1 – 1.4 20 0 5 V V µA µA pF ILE Digital input (PECL) Digital input voltage Digital input current VIH VIL IIH IIL VFS = 1000mV ∗2 DVCC1 – 1.05 DVCC1 – 3.2 0 –30 VIH = DVCC1 – 0.8V VIL = DVCC1 – 1.6V Digital input capacitance Digital input (TTL) Digital input voltage Threshold voltage Digital input current VIH VIL...

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