SP4T SOI Antenna Diversity Switch, and 3G/LTE Tx Switch CXA2984GC Description The CXA2984 is the SP4T antenna diversity switch for WCDMA, and Tx switch for 3G/LTE applications.. The CXA2984 has a 1.8 V CMOS compatible decoder. The SONY Silicon On Insulator (SOI) technology is used for low insertion loss. Features ◆Low Insertion loss : 0.37 dB(typ.) @800 MHz 0.45 dB(typ.) @2 GHz 0.50 dB(typ.) @2.7 GHz ◆No DC Blocking Capacitors (except sourcing DC bias) ◆Solder Bump Bare Die(SBBD): Bump Pitch=0.4 mm ◆Small Flip-Chip Size : 1.1 mm x 1.5 mm x 0.35 mm Typ. ◆Lead-Free and RoHS compliant ◆Applications: Diversity Switch, 3G/LTE Tx Switch Structure SOI CMOS MMIC This IC is ESD sensitive device. Special handling precautions are required

Absolute Maximum Ratings ◆ Supply voltage ◆ Maximum input ◆ Operating temperature

Electrical Characteristics (VDD=2.5V, Ta=25℃) Item Inter Modulation Product Power in Rx Band Control Current Ictl Supply Current Idd Switching Speed Swt Pin = 26 dBm, freq = 704 to 915 MHz Pin = 26 dBm, freq = 1710 to 1910 MHz Pin = 26 dBm, freq = 1920 to 1980 MHz Pin = 26 dBm, freq = 2500 to 2570 MHz Pin on RF: 20 dBm, 835 MHz, Pin on ANT: -15 dBm, 45 MHz Pin on RF: 20 dBm, 1745 MHz, Pin on ANT: -15 dBm, 95 MHz Pin on RF: 20 dBm, 1880 MHz, Pin on ANT: -15 dBm, 80 MHz Pin on RF: 20 dBm, 1950 MHz, Pin on ANT: -15 dBm, 190 MHz Pin on RF: 20 dBm, 835 MHz, Pin on ANT: -15 dBm, 790 MH Pin on RF: 20...

Recommended Circuit *1: No DC blocking capacitors are required on all RF ports. *2: DC levels of all RF ports are GND. *3: L1 (27 nH) and C1 (6.8 pF) are recommended on Ant port for ESD protection. *4: C2(100 pF) is recommended on VDD pin for Decoupling Capacitor.

Device specification ■Pin counts : lOPin ■Solder Bump height: 0.15 mm •Solder Bump ball size : q>0.2 mm •Solder Bump pitch : 0.4 mm ■Land size (Resist Open area) : (f>200 um : Resist open : Solder print area (Metal mask thickness : 110 um)

CROSS SECT I ON OF JNDER BALL PACKAGE STRUCTURE

8m WIDTH EMBOSSED TAPING THIS SPECIFICATION D E SCR I BE S THE EMBOSSED TAPING FOR SMD (SURFACE MOUNTED DEVICE) IC S, FOR SHIPMENT.THIS SPECIFICATION IS BASED ON THE STIPULATIONS OF JAPAN ELECTRONICS AM) INFCRMfi.TIO1! TECHNOLOGY INDU5TRIE5 ASSOCIATION(JEITA1. JIS CC806-L AND ELECTRONIC INDUSTRIES ASSOCIATION EIA-+81. PRODUCT NAME TAPING SYMBOL 1I3TE)I.THE H MEASUREMENT IITHDJI INDICATION IS ASSUMED TO BE 0. 3nn MAX. GENERAL TCLE^ANCE- ±0. 2 !. THE FEED HOLE CUMULATIVE PITCH ERROR IS ASSUMED AT+O. 2nm/ 1 0 PITCH. IN IT :mm <* 1 BOmm P LAST I C REEL

ii TYPE NO. ( m j cumcTEfis I in SECTion c.___ I FOff HOftE THAN j CHARACTERS FOLLOW KULES FDS ABBKiVlflTI QMS, ) ?) MANUFAC1JR M", IF.AR ( I CHARACTFR ) K SFCTI Qj| B 3) ASSEHBH LOCATJiJjLCJJlEjJ, CHARACTER ) IN SECTION D. 0 SEE IAL CODE I M Ait 3 CHARACTER > IN SECTIP_L_

Moisture Sensitivity Moisture Sensitivity Level for this part is MSL = 2

Note Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits