World’s First DDR5 RDIMMs For server and networking solutions The latest DDR5 DRAM standard turbo-boosts RDIMM module performance and technology for the era of AI and Big Data. SK hynix expects its DDR5 RDIMMs to reach over 8,000Mbps in data rates with research into continued speed enhancements. Features Sub-Channel A DRAM Independent Data 32bit Parity 8bit Channel A Independent Data 32bit Parity 8bit Channel B | New Sub-channel DRAM Architecture The dual sub-channel structure on DDR5 RDIMM allows for an increase in CA pin count, with seven CA buses per sub-channel running at double data rate (DDR) from host to RCD and 14 on a single data rate (SDR) interface from RCD to DRAM, effectively doubling bandwidth over a single DDR4 channel. In-DRAM ECC on the DIMM offloads the system’s error correction burden and considerably improves Reliability, Availability, and Serviceability (RAS). | Stable Power Management On-board power management IC (PMIC) eliminates the need for external voltage regulation and ensures more stable power provision to the DRAM. 1 of 2 | World’s First DDR5 RDIMMs : For server and networking solutions https://product.skhynix.com www.linkedin.com/company/sk-hynix Parity Cell

| Diverse Capacities Supported Higher and flexible single-die density on DDR5, starting from 16Gb and upwards to 24Gb and 32Gb, enables a wide range of low-power, high-capacity DIMMs to be configured. DIMM solution Product Details | DDR5 RDIMM Module Density Package Material Lead&Halogen Free Package Type Data Rate Data Width Performance gains on DDR5 RDIMM enable the same system performance to be reached with fewer servers – delivering the solution envisioned in SK hynix’s Memory ForEST* initiative. *Memory ForEST: (https://product.skhynix.com/support/forest.go) Machine Learning 2 of 2 | World’s...