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Description SK hynix Unbuffered Small Outline DDR4 SDRAM DIMMs (Unbuffered Small Outine Double Data Rate Synchronous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use DDR4 SDRAM devices. These DDR4 SDRAM Unbuffered Small Outline DIMMs are intended for use as main memory when installed in systems such as micro servers and mobile personal computres.

CAS_n is a multiplexed function with A15. RAS_n is a multiplexed function with A16. WE_n is a multiplexed function with A14.

D0 Serial PD with Thermal sensor D2 VDDSPD " VPP" VDD " V-TT-VREFCA- 1. Unless otherwize noted, resistor values are 15^+5%. 2. ZQ resistors are 240^+1%.For all other resistor values refer to the appropriate wiring diagram.

DQS_t ^ % Serial PD with Thermal sensor Note: 1. Unless otherwize noted, resistor values are 15 Q±5%. 2. ZQ resistors are 240Q±1%.For all other resistor values refer to the appropriate wiring diagram. 3. To connect the SPD A2 input to the edge connector pin 166 install R1. To tie the SPD input A2 to ground install R2. Do not install both R1 and R2. The values for R1 and R2 are not critical. Any value less than 100 Ohms may be used.

DQS_t dqs_c D4 i DQ [7:0] DM_n/DBI_n DQS_t dqs_c D8 i DQ [7:0] DM_n/DBI_n Serial PD with Thermal sensor Note: 1. Unless otherwize noted, resistor values are 15 Q±5%. 2. ZQ resistors are 240Q±1%.For all other resistor values refer to the appropriate wiring diagram. 3. To connect the SPD A2 input to the edge connector pin 166 install R1. To tie the SPD input A2 to ground install R2. Do not install both R1 and R2. The values for R1 and R2 are not critical. Any value less than 100 Ohms may be used.

DQS_t ^ = S Serial PD with Thermal sensor Vss Note: 1. Unless otherwize noted, resistor values are 15 ^+5%. 2. ZQ resistors are 240^+1%.For all other resistor values refer to the appropriate wiring diagram. 3. SDRAMs for ODD ranks (D8 to D15), which are placed on the back side of the module use the address mirroing for A4-A3, A6-A5, A8-A7, A13-A11, BA1-BA0 and BG1-BG0. More detail can be found in the DDR4 SODIMM Common Section of the Design Specification.

DQS_t DQS_c ' ■ _ DQS_t DQS_c ' - Serial PD with Thermal sensor 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. Unless otherwize noted, resistor values are 15Q±5%. 3. See the Net Structure diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240Q±1%.For all other resistor values refer to the appropriate wiring diagram.

Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measure ment conditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC case temperature. Full specifications are guaranteed in this range, but the following additional conditions...

Recommended DC Operating Conditions Symbol 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

Single-ended AC & DC input levels for Command and Address Symbol 1. See "Overshoot and Undershoot Specifications" 2. The AC peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by more than ± 1% VDD (for reference : approx. ± 12mV)

AC and DC Input Measurement Levels: VREF Tolerances The DC-tolerance limits and ac-noise limits for the reference voltages VREFCA is illustrated in Figure below. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table X. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD. voltage Illustration of VREF(DC) tolerance and VREF AC-noise limits The voltage levels for setup and hold time measurements...

AC and DC Logic Input Levels for Differential Signals Differential signal definition tDVAC VIH.DIFF.AC.MIN Differential Input Voltage (CK-CK) (CK_t - CK_c) VIL.DIFF.AC.MAX tDVAC time NOTE: 1. Differential signal rising edge from VIL.DIFF.MAX to VIH.DIFF.MIN must be monotonic slope. 2. Differential signal falling edge from VIH.DIFF.MIN to VIL.DIFF.MAX must be monotonic slope. Definition of differential ac-swing and “time above ac-level” tDVAC

Single-ended requirements for differential signals Each individual component of a differential signal (CK_t, CK_c) has also to comply with certain requirements for single-ended signals. CK_t and CK_c have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH.CA(AC) / VIL.CA(AC) ) for ADD/CMD signals) in every half-cycle. Note that the applicable ac-levels for ADD/CMD might be different per speed-bin etc. E.g., if Different value than VIH.CA(AC100)/VIL.CA(AC100) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK_t and CK_c...

2. Vih(AC)/Vil(AC) for ADD/CMD is based on Vrefca; 3. These values are not defined, however the single-ended signals CK_t - CK_c need to be within the respective limits (Vih.ca(DC) max, VIL.CA(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot.

Address and Control Overshoot and Undershoot specifications AC overshoot/undershoot specification for Address, Command and Control pins Specification Parameter Maximum peak amplitude above VDD Absolute Max allowed for overshoot area Delta value between VDD Absolute Max and VDD Max allowed for overshoot area Maximum peak amplitude allowed for undershoot area Maximum overshoot area per 1tCK Above Absolute Max Maximum overshoot area per 1tCK Between Absolute Max Maximum undershoot area per 1tCK Below VSS Overshoot Area above VDD Absolute Max VDD Absolute Max Overshoot Area Between VDD Absolute Max...